參數(shù)資料
型號: CY7C43684
廠商: Cypress Semiconductor Corp.
英文描述: 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
中文描述: 16K的x36 x2雙向同步FIFO瓦特/總線匹配(16K的x36 x2雙向同步先進(jìn)先出帶總線匹配)
文件頁數(shù): 26/37頁
文件大小: 581K
代理商: CY7C43684
CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
26
PRELIMINARY
Note:
47. If Port B is configured for word size, data can be written to the Mail1 register using A
(A
are
don
t care
inputs). In this first case B
0
will have
valid data (B
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A
0
8
(A
9
35
are
don
t care
inputs). In this second case, B
0
8
will have valid data (B
9
35
will be indeterminate).
Switching Waveforms
(continued)
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
DH
t
DS
W1
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
CLKA
CSA
W/RA
MBA
ENA
A
0
35
CLKB
MBF1
CSB
W/RB
MBB
ENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)
[47]
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