參數(shù)資料
型號(hào): CY7C43684
廠商: Cypress Semiconductor Corp.
英文描述: 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
中文描述: 16K的x36 x2雙向同步FIFO瓦特/總線匹配(16K的x36 x2雙向同步先進(jìn)先出帶總線匹配)
文件頁(yè)數(shù): 10/37頁(yè)
文件大?。?/td> 581K
代理商: CY7C43684
CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
10
PRELIMINARY
Notes:
13. Partial Reset is performed in the same manner for FIFO2.
14. MRS1 must be HIGH during Partial Reset.
15. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
16. t
is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than t
SKEW1
, then FFB/IRB may transition HIGH one cycle later than shown.
Switching Waveforms
(continued)
FIFO1 Partial Reset (CY Standard and FWFT Modes)
t
RSF
t
RSF
t
RSF
t
RSTS
t
RSTH
CLKA
CLKB
PRS1
FFA/IRA
EFB/ORB
AEB
AFA
MBF1
[13, 14]
t
WFF
t
RSF
t
RSF
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
t
WFF
t
FSS
t
DS
t
FSS
t
FSH
t
FSH
t
ENS
t
ENH
t
DH
t
SKEW1[16]
AFA Offset (Y1)
AFB Offset (Y2)
First Word to FIFO1
CLKA
MRS1, MRS2
SPM
FS1/SEN,
FS0/SD
FFA/IRA
ENA
A
0
35
CLKB
FFB/IRB
[15]
AEB Offset (X1)
AEA Offset (X2)
相關(guān)PDF資料
PDF描述
CY7C43636 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進(jìn)先出)
CY7C43626 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進(jìn)先出)
CY7C43646 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進(jìn)先出)
CY7C43666 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進(jìn)先出)
CY7C43686 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進(jìn)先出)
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