參數(shù)資料
型號: CY7C43684
廠商: Cypress Semiconductor Corp.
英文描述: 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進先出帶總線匹配)
中文描述: 16K的x36 x2雙向同步FIFO瓦特/總線匹配(16K的x36 x2雙向同步先進先出帶總線匹配)
文件頁數(shù): 11/37頁
文件大小: 581K
代理商: CY7C43684
CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
11
PRELIMINARY
Notes:
17. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
18. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).
19. Written to FIFO1.
Switching Waveforms
(continued)
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes)
t
FSS
t
SPH
t
SENS
t
SENH
t
SENH
t
SENS
t
SDH
t
SDS
t
SDH
t
SDS
t
SKEW1[16]
t
WFF
AFA Offset (Y1) MSB
t
FSS
t
FSH
t
WFF
CLKA
MRS1,
MRS2
SPM
FFA/IRA
FS1/SEN
CLKB
FFA/IRA
[17]
FS0/SD
[18]
AEA Offset (X2) LSB
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
DS
t
DH
t
ENS
t
ENH
t
ENS
t
ENH
HIGH
W1
[19]
W2
[19]
t
CLK
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A
0
35
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
相關(guān)PDF資料
PDF描述
CY7C43636 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進先出)
CY7C43626 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進先出)
CY7C43646 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進先出)
CY7C43666 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進先出)
CY7C43686 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進先出)
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