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參數(shù)資料
| 型號： | CY7C43684 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進先出帶總線匹配) |
| 中文描述： | 16K的x36 x2雙向同步FIFO瓦特/總線匹配（16K的x36 x2雙向同步先進先出帶總線匹配） |
| 文件頁數(shù)： | 3/37頁 |
| 文件大?。?/td> | 581K |
| 代理商： | CY7C43684 |
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CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
3
PRELIMINARY
Functional Description
The CY7C436X4 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports clock frequencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent 256/512/1K/4K/
16K x 36 dual-port SRAM FIFOs on board each chip buffer
data in opposite directions. FIFO data on Port B can be input
and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big
or Little Endian configurations.
The CY7C436X4 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are in-
dependent of one another and can be asynchronous or coin-
cident. The enables for each port are arranged to provide a
simple bidirectional interface between microprocessors and/or
buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers
’
width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436X4: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array, config-
ures the FIFO for Big or Little Endian byte arrangement and
selects serial flag programming, parallel flag programming, or
one of the three possible default flag offset settings, 8, 16, or
64. Each FIFO has its own independent Master Reset pin,
MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings ex-
isting prior to Partial Reset (i.e., programming method and par-
tial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. Each FIFO has its own, indepen-
dent Partial Reset pin, PRS1 and PRS2.
The CY7C436X4 have two modes of operation: In the CY
Standard Mode, the first word written to an empty FIFO is de-
posited into the memory array. A read operation is required to
access that word (along with all other words residing in mem-
ory). In the First-Word Fall-Through Mode
(FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears au-
tomatically on the outputs, no read operation required (never-
theless, accessing subsequent words does necessitate a for-
mal read request). The state of the BE/FWFT pin during FIFO
operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready flag (EFA/
ORA and EFB/ORB) and a combined Full/Input Ready flag
(FFA/IRA and FFB/IRB). The EF and FF functions are selected
in the CY Standard mode. EF indicates whether the memory
is full or not. The IR and OR functions are selected in the First-
Word Fall-Through mode. IR indicates whether or not the FIFO
has available memory locations. OR shows whether the FIFO
has data available for reading or not. It marks the presence of
valid data on the outputs.
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB indicate when a selected number of words writ-
ten to FIFO memory achieve a predetermined
“
almost empty
state.
”
AFA and AFB indicate when a selected number of
words written to the memory achieve a predetermined
“
almost
full state.
”
IRA, IRB, AFA, and AFB are synchronized to the port clock that
writes data into its array. ORA, ORB, AEA, and AEB are syn-
chronized to the port clock that reads data from its array. Pro-
grammable offset for AEA, AEB, AFA, and AFB are loaded in
parallel using Port A or in serial via the SD input. Three default
offset settings are also provided. The AEA and AEB threshold
can be set at 8, 16, or 64 locations from the empty boundary
and AFA and AFB threshold can be set at 8, 16, or 64 locations
from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. If at any time the FIFO is not actively performing a
function, the chip will automatically power down. During the
power-down state, supply current consumption (I
CC
) is at a
minimum. Initiating any operation (by activating control inputs)
will immediately take the device out of the power-down state.
Retransmit feature is available on these devices.
The CY7C436X4 are characterized for operation from 0
°
C to
70
°
C. Input ESD protection is greater than 2001V, and latch-
up is prevented by the use of guard rings.
Selection Guide
CY7C43624/34/44/64/84
–
7
133
6
7.5
3
0
6
100
CY7C43624/34/44/64/84
–
10
100
8
10
4
0
8
100
CY7C43624/34/44/64/84
15
66.7
10
15
5
0
8
100
100
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
CC1
) (mA)
Commercial
Industrial
CY7C43624
256 x 36 x2
128 TQFP
CY7C43634
512 x 36 x2
128 TQFP
CY7C43644
1K x 36 x2
128 TQFP
CY7C43664
4K x 36 x2
128 TQFP
CY7C43684
16K x 36 x2
128 TQFP
Density
Package
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43636 | 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進先出) |
| CY7C43626 | 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進先出) |
| CY7C43646 | 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進先出) |
| CY7C43666 | 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進先出) |
| CY7C43686 | 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43684AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk |
| CY7C43686-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43686AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP |
| CY7C439-40DMB | 制造商:Cypress Semiconductor 功能描述: |
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