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參數(shù)資料
| 型號(hào)： | CY7C43684 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 16K的x36 x2雙向同步FIFO瓦特/總線匹配（16K的x36 x2雙向同步先進(jìn)先出帶總線匹配） |
| 文件頁(yè)數(shù)： | 18/37頁(yè) |
| 文件大?。?/td> | 581K |
| 代理商： | CY7C43684 |
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CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
18
PRELIMINARY
Notes:
28. If Port B size is word or byte, t
is referenced to the rising CLKB edge that writes the last word or byte of the long-word, respectively.
29. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than t
SKEW1
, then the transition of ORA HIGH and
load of the first word to the output register may occur one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENS
t
ENH
t
A
W1
LOW
t
DH
LOW
HIGH
FIFO2 Empty
LOW
LOW
LOW
Old Data in FIFO2 Output Register
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
SKEW1
[29]
t
CLK
t
DS
CLKB
CSB
W/RB
MBB
ENB
FFB/IRB
B
0
–
35
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A
0
–
35
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
[28]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43684AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk |
| CY7C43686-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43686AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP |
| CY7C439-40DMB | 制造商:Cypress Semiconductor 功能描述: |
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