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參數(shù)資料
| 型號： | CY7C43662AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進先出) |
| 中文描述： | 3.3 4K的x36 x2雙向同步FIFO（3.3 4K的x36 x2雙向同步先進先出） |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 458K |
| 代理商： | CY7C43662AV |
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CY7C43642AV
CY7C43662AV/CY7C43682AV
3
PRELIMINARY
Functional Description
The CY7C436X2AV is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports clock frequencies up to133 MHz and has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions.
The CY7C436X2AV is a synchronous (clocked) FIFO, mean-
ing each port employs a synchronous interface. All data trans-
fers through a port are gated to the LOW-to-HIGH transition of
a port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or co-
incident. The enables for each port are arranged to provide a
simple bidirectional interface between microprocessors and/or
buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers
’
width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Master Reset initializes the read and write pointers to the first
location of the memory array, and selects parallel flag pro-
gramming, or one of the three possible default flag offset set-
tings, 8, 16, or 64. Each FIFO has its own independent Master
Reset pin, RST1 and RST2.
The CY7C436X2AV have two modes of operation: In the CY
Standard Mode, the first word written to an empty FIFO is de-
posited into the memory array. A read operation is required to
access that word (along with all other words residing in mem-
ory). In the First-Word Fall-Through Mode
(FWFT), the first
word (36-bit wide) written to an empty FIFO appears automat-
ically on the outputs, no read operation required (nevertheless,
accessing subsequent words does necessitate a formal read
request). The state of the FWFT/STAN pin during FIFO oper-
ation determines the mode in use.
Each FIFO has a combined Empty/Output Ready flag (EFA/
ORA and EFB/ORB) and a combined Full/Input Ready flag
(FFA/IRA and FFB/IRB). The EF and FF functions are selected
in the CY Standard Mode. EF indicates whether the memory
is full or not. The IR and OR functions are selected in the First-
Word Fall-Through Mode. IR indicates whether or not the FIFO
has available memory locations. OR shows whether the FIFO
has data available for reading or not. It marks the presence of
valid data on the outputs.
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB indicate when a selected number of words writ-
ten to FIFO memory achieve a predetermined
“
almost empty
state.
”
AFA and AFB indicate when a selected number of
words written to the memory achieve a predetermined
“
almost
full state.
”
IRA, IRB, AFA, and AFB are synchronized to the port clock that
writes data into its array. ORA, ORB, AEA, and AEB are syn-
chronized to the port clock that reads data from its array. Pro-
grammable offset for AEA, AEB, AFA, and AFB are loaded in
parallel using Port A. Three default offset settings are also pro-
vided. The AEA and AEB threshold can be set at 8, 16, or 64
locations from the empty boundary and AFA and AFB thresh-
old can be set at 8, 16, or 64 locations from the full boundary.
All these choices are made using the FS0 and FS1 inputs dur-
ing Master Reset.
Two or more devices may be used in parallel to create wider
data paths. If at any time the FIFO is not actively performing a
function, the chip will automatically power down. During the
Power Down state, supply current consumption (I
CC
) is at a
minimum. Initiating any operation (by activating control inputs)
will immediately take the device out of the Power Down state.
The CY7C436X2AV are characterized for operation from 0
°
C
to 70
°
C. Input ESD protection is greater than 2001V, and latch-
up is prevented by the use of guard rings.
Selection Guide
CY7C43642/
62/82AV
–
7
133
6
7.5
3
0
6
60
CY7C43642/
62/82AV
–
10
100
8
10
4
0
8
60
CY7C43642/
62/82AV
–
15
66.7
10
15
5
0
10
60
60
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
CC1
) (mA)
Commercial
Industrial
CY7C43642AV
1K x 36 x2
120 TQFP
CY7C43662AV
4K x 36 x2
120 TQFP
CY7C43682AV
16K x 36 x2
120 TQFP
Density
Package
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43682AV | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進先出) |
| CY7C43663AV | 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進先出帶總線匹配) |
| CY7C43683AV | 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進先出帶總線匹配) |
| CY7C43664AV | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 x2 雙向同步先進先出帶總線匹配) |
| CY7C43644AV | 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進先出帶總線匹配) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43663-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
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