參數(shù)資料
型號(hào): CY7C43662AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進(jìn)先出)
中文描述: 3.3 4K的x36 x2雙向同步FIFO(3.3 4K的x36 x2雙向同步先進(jìn)先出)
文件頁數(shù): 14/30頁
文件大小: 458K
代理商: CY7C43662AV
CY7C43642AV
CY7C43662AV/CY7C43682AV
14
PRELIMINARY
Note:
19. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENS
t
ENH
t
A
t
DS
W1
LOW
t
DH
HIGH
HIGH
FIFO1 Empty
LOW
HIGH
LOW
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[19]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A
0
35
CLKB
EFB/ORB
CSB
W/RB
MBB
ENB
B
0
35
EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (CY Standard Mode)
[19]
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