參數(shù)資料
型號(hào): CY7C43662AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進(jìn)先出)
中文描述: 3.3 4K的x36 x2雙向同步FIFO(3.3 4K的x36 x2雙向同步先進(jìn)先出)
文件頁(yè)數(shù): 19/30頁(yè)
文件大?。?/td> 458K
代理商: CY7C43662AV
CY7C43642AV
CY7C43662AV/CY7C43682AV
19
PRELIMINARY
Note:
25. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of IRB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
LOW
LOW
HIGH
FIFO2 Full
LOW
LOW
t
ENS
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[25]
t
DH
t
DS
t
ENH
t
ENS
Previous Word in FIFO2 Output Register
Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A
0
35
CLKB
FFB/IRB
CSB
W/RB
MBB
ENB
B
0
35
IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
相關(guān)PDF資料
PDF描述
CY7C43682AV 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出)
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