參數(shù)資料
型號： CY7C43662AV
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進先出)
中文描述： 3.3 4K的x36 x2雙向同步FIFO（3.3 4K的x36 x2雙向同步先進先出）
文件頁數(shù)： 26/30頁
文件大?。?/td> 458K
代理商： CY7C43662AV
CY7C43642AV
CY7C43662AV/CY7C43682AV
26
PRELIMINARY
siding in the FIFO
’
s memory array is clocked to the output reg-
ister only when a read is selected using the port
’
s Chip Select,
Write/Read select, Enable, and Mailbox select.
When operating the FIFO in CY Standard Mode, regardless of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO
’
s memory array is clocked to the output register only
when a read is selected using the port
’
s Chip Select, Write/
Read select, Enable, and Mailbox select.
Synchronized Flags
Each FIFO is synchronized to its port clock through at least
two flip-flop stages. This is done to improve flag-signal reliabil-
ity by reducing the probability of the metastable events when
CLKA and CLKB operate asynchronously to one another. EFA/
ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.
EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to
CLKB.
Table 4
and
Table 5
show the relationship of each port
flag to FIFO1 and FIFO2.
Empty/Output Ready Flags (EFA/ORA, EFB/ORB)
These are dual-purpose flags. In the FWFT Mode, the Output
Ready (ORA, ORB) function is selected. When the Output
Ready flag is HIGH, new data is present in the FIFO output
register. When the Output Ready flag is LOW, the previous
data word is present in the FIFO output register and attempted
FIFO reads are ignored.
In the CY Standard Mode, the Empty Flag (EFA, EFB) function
is selected. When the Empty Flag is HIGH, data is available in
the FIFO
’
s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word is present
in the FIFO output register and attempted FIFO reads are ig-
nored.
The Empty/Output Ready flag of a FIFO is synchronized to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is increment-
ed each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write pointer and read pointer comparator that indicates when
the FIFO SRAM status is empty, empty+1, or empty+2.
In FWFT Mode, from the time a word is written to a FIFO, it can
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. There-
fore, an Output Ready flag is LOW if a word in memory is the
next data to be sent to the FIFO output register and three cy-
cles have not elapsed since the time the word was written. The
Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs, si-
multaneously forcing the Output Ready flag HIGH and shifting
the word to the FIFO output register.
In the CY Standard Mode, from the time a word is written to a
FIFO, the Empty Flag will indicate the presence of data avail-
able for reading in a minimum of two cycles of the Empty flag
synchronizing clock. Therefore, an Empty flag is LOW if a word
in memory is the next data to be sent to the FIFO output reg-
ister and two cycles have not elapsed since the time the word
was written. The Empty flag of the FIFO remains LOW until the
second LOW-to-HIGH transition of the synchronizing clock oc-
curs, forcing the Empty flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time t
SKEW1
or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FFA/IRA, FFB/IRB)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IRA and IRB) function is selected. In CY Standard Mode, the
Full Flag (FFA and FFB) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
attempted writes to the FIFO are ignored.
The Full/Input Ready flag of a FIFO is synchronized to the port
clock that writes data to its array. For both FWFT and CY Stan-
dard modes, each time a word is written to a FIFO, its write
pointer is incremented. The state machine that controls a Full/
Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is full,
full
–
1, or full
–
2. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a mini-
mum of two cycles of the Full/Input Ready flag synchronizing
clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have elapsed since the next memory write location has been
read. The second LOW-to-HIGH transition on the Full/Input
Ready flag synchronizing clock after the read sets the Full/
Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time t
SKEW1
or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AEA, AEB)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, almost empty+1, or almost empty+2.
The Almost Empty state is defined by the contents of register
X1 for AEB and register X2 for AEA. These registers are load-
ed with preset values during a FIFO reset, programmed from
Port A, or programmed serially (see Almost Empty flag and
Almost Full flag offset programming above). An Almost Empty
flag is LOW when its FIFO contains X or less words and is
HIGH when its FIFO contains (X+1) or more words. A data
word present in the FIFO output register has been read from
memory.
Two LOW-to-HIGH transitions of the Almost Empty flag syn-
chronizing clock are required after a FIFO write for its Almost
Empty flag to reflect the new level of fill. Therefore, the Almost
Full flag of a FIFO containing (X+1) or more words remains
LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An
Almost Empty flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO write that
fills memory to the (X+1) level. A LOW-to-HIGH transition of an
Almost Empty flag synchronizing clock begins the first syn-
chronization cycle if it occurs at time t
SKEW2
or greater after
the write that fills the FIFO to (X+1) words. Otherwise, the sub-
sequent synchronizing clock cycle may be the first synchroni-
zation cycle.
相關(guān)PDF資料
PDF描述
CY7C43682AV 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進先出)
CY7C43663AV 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進先出帶總線匹配)
CY7C43683AV 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進先出帶總線匹配)
CY7C43664AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 x2 雙向同步先進先出帶總線匹配)
CY7C43644AV 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進先出帶總線匹配)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C43663-15AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43664-7AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43682-15AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43683-10AI 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43683AV-15AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk
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