參數(shù)資料
型號: CY7C43662AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進(jìn)先出)
中文描述: 3.3 4K的x36 x2雙向同步FIFO(3.3 4K的x36 x2雙向同步先進(jìn)先出)
文件頁數(shù): 15/30頁
文件大小: 458K
代理商: CY7C43662AV
CY7C43642AV
CY7C43662AV/CY7C43682AV
15
PRELIMINARY
Notes:
20. t
SKEW1
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
21. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than t
SKEW1
, then the transition of ORA HIGH and
load of the first word to the output register may occur one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENS
t
ENH
t
A
W1
LOW
t
DH
LOW
HIGH
FIFO2 Empty
LOW
LOW
LOW
Old Data in FIFO2 Output Register
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
SKEW1[21]
t
CLK
t
DS
CLKB
CSB
W/RB
MBB
ENB
FFB/IRB
B
0
35
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A
0
35
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
[20]
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