參數(shù)資料
型號(hào): CY7C43682AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出)
中文描述: 3.3 16K的x36 x2雙向同步FIFO(3.3 16K的x36 x2雙向同步先進(jìn)先出)
文件頁數(shù): 1/30頁
文件大?。?/td> 458K
代理商: CY7C43682AV
CY7C43642AV
CY7C43662AV/CY7C43682AV
3.3V 1K/4K/16K x36 x2 Bidirectional
Synchronous FIFO
Fully asynchronous and simultaneous read and write
operation permitted
Mailbox bypass register for each FIFO
Parallel Programmable Almost Full and Almost Empty
flags
Retransmit function
Standard or FWFT mode user selectable
120-pin TQFP packaging
3.3V pin-compatible, feature enhanced, density up-
grade to IDT723622/32/42 family
Easily expandable in width and depth
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
September 3, 1999
V
Features
3.3V high-speed, low-power, bidirectional, First-In First-
Out (FIFO) memories
1K x36 x2 (CY7C43642AV)
4K x36 x2 (CY7C43662AV)
16K x36 x2 (CY7C43682AV)
0.25-micron CMOS for optimum speed/power
High-speed 133-MHz operation (7.5-ns read/write cycle
times)
Low power
—I
CC
= 60 mA
—I
SB
= 12 mA
Logic Block Diagram
Port A
Control
Logic
Port B
Control
Logic
Mail1
Register
I
R
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable
Flag Offset
Registers
Timing
Mode
Status
Flag Logic
Write
Pointer
Read
Pointer
1K/4K/16K
x36
Dual Ported
Memory
1K/4K/16K
x36
Dual Ported
Memory
Mail2
Register
O
R
I
R
FIFO1,
Mail1
Reset
Logic
FIFO2,
Mail2
Reset
Logic
CLKA
CSA
W/RA
ENA
MBA
RT2
MRST1
FFA/IRA
AFA
FS0
FS1
A
0–35
EFA/ORA
AEA
MBF2
MRST2
FFB/IRB
AFB
FWFT/STAN
B
0–35
CLKB
CSB
W/RB
ENB
MBB
RT1
EFB/ORB
AEB
MBF1
O
R
相關(guān)PDF資料
PDF描述
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CY7C43683AV 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進(jìn)先出帶總線匹配)
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CY7C43684AV 3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
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