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參數(shù)資料
| 型號(hào)： | CY7C43682AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出) |
| 中文描述： | 3.3 16K的x36 x2雙向同步FIFO（3.3 16K的x36 x2雙向同步先進(jìn)先出） |
| 文件頁(yè)數(shù)： | 27/30頁(yè) |
| 文件大?。?/td> | 458K |
| 代理商： | CY7C43682AV |
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CY7C43642AV
CY7C43662AV/CY7C43682AV
27
PRELIMINARY
Almost Full Flags (AFA, AFB)
The Almost Full flag of a FIFO is synchronized to the port clock
that writes data to its array. The state machine that controls an
Almost Full flag monitors a write pointer and read pointer com-
parator that indicates when the FIFO SRAM status is almost
full, almost full
–
1, or almost full
–
2. The Almost Full state is
defined by the contents of register Y1 for AFA and register Y2
for AFB. These registers are loaded with preset values during
a FIFO reset, programmed from Port A, or programmed seri-
ally (see Almost Empty flag and Almost Full flag offset pro-
gramming above). An Almost Full flag is LOW when the num-
ber of words in its FIFO is greater than or equal to (1024
–
Y),
(4096
–
Y), or (16384
–
Y) for the CY7C436X2AV respectively.
An Almost Full flag is HIGH when the number of words in its
FIFO is less than or equal to [1024
–
(Y+1)], [4096
–
(Y+1)], or
[16384
–
(Y+1)], for the CY7C436X2AV respectively. Note that
a data word present in the FIFO output register has been read
from memory.
Two LOW-to-HIGH transitions of the Almost Full flag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384
–
(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words in memory to [1024/4096/16384
–
(Y+1)]. An Almost Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the num-
ber of words in memory to [1024/4096/16384
–
(Y+1)]. A LOW-
to-HIGH transition of an Almost Full flag synchronizing clock
begins the first synchronization cycle if it occurs at time t
SKEW2
or greater after the read that reduces the number of words in
memory to [1024/4096/16384
–
(Y+1)]. Otherwise, the subse-
quent synchronizing clock cycle may be the first synchroniza-
tion cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2 regis-
ters matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A
0
35
data to the
Mail1 Register when a Port A write is selected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register em-
ploys data lines A
0
35
. If the selected Port A bus size is 18 bits,
then the usable width of the Mail1 Register employs data lines
A
0
17
. (In this case, A
18
35
are don
’
t care inputs.) If the select-
ed Port A bus size is 9 bits, then the usable width of the Mail1
Register employs data lines B
0
8
. (In this case, A
9
35
are don
’
t
care inputs.)
A LOW-to-HIGH transition on CLKB writes B
0
35
data to the
Mail2 Register when a Port B write is selected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register em-
ploys data lines B
0
–
35
. If the selected Port B bus size is 18 bits,
then the usable width of the Mail2 Register employs data lines
B
0
–
17
. (In this case, B
18
–
35
are don
’
t care inputs.) If the select-
ed Port B bus size is 9 bits, then the usable width of the Mail2
Register employs data lines B
0
8
. (In this case, B
9
35
are don
’
t
care inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-
HIGH transition on CLKB when a Port B read is selected by
CSB, W/RB, and ENB with MBB HIGH. For a 36-bit bus size,
36 bits of mailbox data are placed on B
0
–
35
. For an 18-bit bus
size, 18 bits of mailbox data are placed on B
0
–
17
. (In this case,
B
18
–
35
are indeterminate.) For a 9-bit bus size, 9 bits of mail-
box data are placed on B
0
–
8
. (In this case, B
9
–
35
are indeter-
minate.)
The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH
transition on CLKA when a Port A read is selected by CSA, W/
RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A
0
–
35
. For an 18-bit bus size, 18 bits of mailbox data are placed
on A
0
–
17
. (In this case, A
18
–
35
are indeterminate.) For a 9-bit
bus size, 9 bits of mailbox data are placed on A
0
–
8
. (In this
case, A
9
–
35
are indeterminate.)
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at least one word has been read since the last reset
cycle. A LOW pulse on RT1, RT2 resets the internal read point-
er to the first physical location of the FIFO. CLKA and CLKB
may be free running but must be disabled during and t
RTR
after
the retransmit pulse. With every valid read cycle after retrans-
mit, previously accessed data is read and the read pointer is
incremented until it is equal to the write pointer. Flags are gov-
erned by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to the
FIFO after activation of RT1, RT2 are transmitted also.
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CY7C43686-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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