- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379094 > CY7C43682AV (Cypress Semiconductor Corp.) 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出) PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C43682AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出) |
| 中文描述： | 3.3 16K的x36 x2雙向同步FIFO（3.3 16K的x36 x2雙向同步先進(jìn)先出） |
| 文件頁數(shù)： | 25/30頁 |
| 文件大?。?/td> | 458K |
| 代理商： | CY7C43682AV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁
CY7C43642AV
CY7C43662AV/CY7C43682AV
25
PRELIMINARY
Signal Description
Reset (RST1, RST2)
Each of the two FIFO memories of the CY7C436X2AV under-
goes a complete reset by taking its associated Master Reset
(RST1, RST2) input LOW for at least four Port A clock (CLKA)
and four Port B clock (CLKB) LOW-to-HIGH transitions. The
Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the internal read and write pointers
and forces the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW,
the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFB) HIGH. A Master Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Master Reset, the FIFO
’
s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation. A Master Re-
set must be performed on the FIFO after power up, before data
is written to its memory.
A LOW-to-HIGH transition on a FIFO reset (RST1, RST2) in-
put latches the values of the Flag select (FS0, FS1) for choos-
ing the Almost Full and Almost Empty offset programming
method (see Almost Empty and Almost Full flag offset pro-
gramming below).
First-Word Fall-Through (FWFT/STAN)
After Master Reset, the FWFT select function is active, permit-
ting a choice between two possible timing modes: CY Stan-
dard Mode or First-Word Fall-Through (FWFT) Mode. Once
the Master Reset (RST1, RST2) input is HIGH, a HIGH on the
FWFT/STAN input at the second LOW-to-HIGH transition of
CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Stan-
dard Mode. This mode uses the Empty Flag function (EFA,
EFB) to indicate whether or not there are any words present in
the FIFO memory. It uses the Full Flag function (FFA, FFB) to
indicate whether or not the FIFO memory has any free space
for writing. In CY Standard mode, every word read from the
FIFO, including the first, must be requested using a formal
read operation.
Once the Master Reset (RST1, RST2) input is HIGH, a LOW
on the FWFT/STAN input during the next LOW-to-HIGH tran-
sition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
FWFT Mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at
the data outputs (A
0
–
35
or B
0
–
35
). It also uses the Input Ready
function (IRA, IRB) to indicate whether or not the FIFO mem-
ory has any free space for writing. In the FWFT mode, the first
word written to an empty FIFO goes directly to data outputs,
no read request necessary. Subsequent words must be ac-
cessed by performing a formal read operation.
Following Master Reset, the level applied to the FWFT/STAN
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X2AV are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Post A Almost Full flag (AFA) offset register is labeled Y1
and the Port B Almost Full flag (AFB) offset register is labeled
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel us-
ing the FIFO
’
s Port A data inputs.
To program the X1, X2, Y1, and Y2 registers from Port A, per-
form a Master Reset on both FIFOs simultaneously with SPM
HIGH and FS0 and FS1 LOW during the LOW-to-HIGH tran-
sition of RST1 and RST2. After this reset is complete, the first
four writes to FIFO1 do not store data in RAM but load the
offset registers in the order Y1, X1, Y2, X2. The Port A data
inputs used by the offset registers are (A
0
–
9
), (A
0
–
11
), or
(A
0
–
13
), for the CY7C436X2AV, respectively. The highest num-
bered input is used as the most significant bit of the binary
number in each case. Valid programming values for the regis-
ters range from 1 to 1012 for the CY7C43642AV; 1 to 4092 for
the CY7C43662AV; 1 to 16380 for the CY7C43682AV. After all
the offset registers are programmed from Port A, the Port B
Full/Input Ready (FFB/IRB) is set HIGH and both FIFOs begin
normal operation.
FS0 and FS1 function the same way in both CY Standard and
FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A
0
–
35
) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A
0
–
35
lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A
0
–
35
lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A
0
–
35
inputs on a LOW-to-
HIGH transition of CLKA when CSA is LOW, W/RA is HIGH,
ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read
from FIFO2 to the A
0
–
35
outputs by a LOW-to-HIGH transition
of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA
is LOW, and EFA/ORA is HIGH (see
Table 2
). FIFO reads and
writes on Port A are independent of any concurrent Port B
operation.
The Port B control signals are identical to those of Port A with
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read select (W/RA). The state of
the Port B data (B
0
–
35
) lines is controlled by the Port B Chip
Select (CSB) and Port B Write/Read select (W/RB). The B
0
–
35
lines are in the high-impedance state when either CSB is
HIGH or W/RB is LOW. The B
0
–
35
lines are active outputs
when CSB is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B
0
–
35
inputs on a LOW-to-
HIGH transition of CLKB when CSB is LOW, W/RB is LOW,
ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is read
from FIFO1 to the B
0
–
35
outputs by a LOW-to-HIGH transition
of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH,
MBB is LOW, and EFB/ORB is HIGH (see
Table 3
). FIFO reads
and writes on Port B are independent of any concurrent Port
A operation.
The set-up and hold time constraints to the port clocks for the
port Chip Selects and Write/Read selects are only for enabling
write and read operations and are not related to high-imped-
ance control of the data outputs. If a port enable is LOW during
a clock cycle, the port
’
s Chip Select and Write/Read select
may change states during the set-up and hold time window of
the cycle.
When operating the FIFO in FWFT Mode and the Output
Ready flag is LOW, the next word written is automatically sent
to the FIFO
’
s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data re-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43663AV | 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43683AV | 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43664AV | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43644AV | 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43684AV | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43684AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk |
| CY7C43686-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。