參數(shù)資料
型號： CY7C43682AV
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出)
中文描述： 3.3 16K的x36 x2雙向同步FIFO（3.3 16K的x36 x2雙向同步先進(jìn)先出）
文件頁數(shù)： 24/30頁
文件大?。?/td> 458K
代理商： CY7C43682AV
CY7C43642AV
CY7C43662AV/CY7C43682AV
24
PRELIMINARY
Notes:
39. Retransmit is performed in the same manner for FIFO2.
40. Clocks are free-running in this case.
41. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
RTR
.
42. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
RTR
to update these flags.
Switching Waveforms
(continued)
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
DH
t
DS
W1
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
FIFO2 Output Register
W1 (Remains valid in Mail2 Register after read)
CLKB
CSB
W/RB
MBB
ENB
B
0
–
35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A
0
35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
FIFO1 Retransmit Timing
ENB
RT1
t
PRT
t
RTR
EFB/FFA
[39, 40, 41, 42]
相關(guān)PDF資料
PDF描述
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