參數(shù)資料
型號(hào)： CY7C43682AV
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出)
中文描述： 3.3 16K的x36 x2雙向同步FIFO（3.3 16K的x36 x2雙向同步先進(jìn)先出）
文件頁(yè)數(shù)： 4/30頁(yè)
文件大?。?/td> 458K
代理商： CY7C43682AV
CY7C43642AV
CY7C43662AV/CY7C43682AV
4
PRELIMINARY
Pin Definitions
Signal Name
Description
I/O
Function
A
0
–
35
AEA
Port A Data
I/O
36-bit bidirectional data port for side A.
Port A Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKA. It is LOW when the number
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2.
AEB
Port B Almost
Empty Flag
O
Programmable Almost Empty flag synchronized to CLKB. It is LOW when the number
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1.
AFA
Port A Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKA. It is LOW when the number of
empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.
AFB
Port B Almost
Full Flag
O
Programmable Almost Full flag synchronized to CLKB. It is LOW when the number of
empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.
B
0
–
35
FWFT/STAN
Port B Data
I/O
36-bit bidirectional data port for side B.
Big Endian/
First-Word Fall-
Through Select
I
During Master Reset. A HIGH on FWFT selects CY Standard mode, a LOW selects
First -Word Fall-Through mode. Once the timing mode has been selected, the level on
FWFT/STAN must be static throughout device operation.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can
be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all
synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can
be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA
Port A Chip
Select
I
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A
0
–
35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B
0
–
35
outputs are in the high-impedance state when CSB is HIGH.
This is a dual-function pin. In the CY Standard Mode, the EFA function is selected. EFA
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A
0
–
35
outputs avail-
able for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.
CSB
Port B Chip
Select
I
EFA/ORA
Port A Empty/
Output Ready
Flag
O
EFB/ORB
Port B Empty/
Output Ready
Flag
O
This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B
0
–
35
outputs avail-
able for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
on Port B.
FFA/IRA
Port A Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the FFA function is selected. FFA
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function
is selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFB/IRB
Port B Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the FFB function is selected. FFB
indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function
is selected. IRB indicates whether or not there is space available for writing to the FIFO2
memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
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