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參數(shù)資料
| 型號： | CY7C342B-20JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 128-Macrocell MAX EPLDs |
| 中文描述： | OT PLD, 33 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 350K |
| 代理商： | CY7C342B-20JI |
CY7C342B
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Document #: 38-03014 Rev. *B
Page 9 of 14
Switching Waveforms
(continued)
t
IN
IO
t
EXP
t
LAC
, t
LAD
t
COMB
t
OD
INPUT PIN
I/O PIN
LOGIC ARRAY
OUTPUT
LOGIC ARRAY
INPUT
ARRAY DELAY
EXPANDER
OUTPUT
PIN
t
Internal Combinatorial
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
t
XZ
t
ZX
t
OD
HIGH IMPEDANCE
STATE
LOGIC ARRAY
DATA FROM
OUTPUT PIN
t
RD
Internal Asynchronous
t
IO
t
AWH
t
AWL
t
F
t
IN
t
IC
t
RSU
t
RH
t
RD
,t
LATCH
t
FD
t
CLR
,t
PRE
t
FD
CLOCK PIN
LOGIC ARRAY
LOGIC ARRAY
CLOCK FROM
DATA FROM
CLOCK INTO
LOGIC ARRAY
REGISTER OUTPUT
TO ANOTHER LAB
t
PIA
LOGIC ARRAY
REGTO LOCAL LAB
t
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C342B-25HC | 128-Macrocell MAX EPLDs |
| CY7C342B-25HI | 128-Macrocell MAX EPLDs |
| CY7C342B-25JC | 128-Macrocell MAX EPLDs |
| CY7C342B-25JI | 128-Macrocell MAX EPLDs |
| CY7C342B-25RC | 128-Macrocell MAX EPLDs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C342B-25HC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um Technology 5V 68-Pin Windowed LCC |
| CY7C342B-25HMB | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 128 Macro Cells 33.3MHz 0.8um (CMOS) Technology 5V |
| CY7C342B-25JC | 制造商: 功能描述: 制造商:Cypress Semiconductor 功能描述: 制造商:undefined 功能描述: |
| CY7C342B-25JI | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um (CMOS) Technology 5V 68-Pin PLCC |
| CY7C342B-25RMB | 制造商:Cypress Semiconductor 功能描述:128-MACROCELL MAX EPLD |
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