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參數(shù)資料
| 型號： | CY7C342B-20JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 128-Macrocell MAX EPLDs |
| 中文描述： | OT PLD, 33 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 350K |
| 代理商： | CY7C342B-20JI |
CY7C342B
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Document #: 38-03014 Rev. *B
Page 6 of 14
Commercial and Industrial External Synchronous Switching Characteristics
Over Operating Range
Parameter
t
PD1
t
PD2
t
SU
t
CO1
t
H
t
WH
t
WL
f
MAX
t
CNT
f
CNT
Description
7C342B-15
Min.
7C342B-20
Min.
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHZ
Max.
15
25
Max.
20
33
Dedicated Input to Combinatorial Output Delay
[3]
I/O Input to Combinatorial Output Delay
[3]
Global Clock Set-Up Time
Synchronous Clock Input to Output Delay
[3]
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency
[4]
Minimum Global Clock Period
Maximum Internal Global Clock Frequency
[5]
10
13
8
9
0
5
5
0
7
7
100
71.4
12
15
83.3
66.7
Commercial and Industrial External Synchronous Switching Characteristics
Over Operating Range
Parameter
t
PD1
t
PD2
t
SU
t
CO1
t
H
t
WH
t
WL
f
MAX
t
CNT
t
ODH
f
CNT
Description
7C342B-25
Min.
7C342B-30
Min.
7C342B-35
Min.
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
MHz
Max.
25
40
Max.
30
45
Max.
35
55
Dedicated Input to Combinatorial Output Delay
[3]
I/O Input to Combinatorial Output Delay
[3]
Global Clock Set-Up Time
Synchronous Clock Input to Output Delay
[3]
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency
[4]
Minimum Global Clock Period
Output Data Hold Time After Clock
Maximum Internal Global Clock Frequency
[5]
15
20
25
14
16
20
0
8
8
0
10
10
50
0
12.5
12.5
40
62.5
20
25
30
2
2
40
2
50
33.3
Commercial and Industrial External Asynchronous Switching Characteristics
Over Operating Range
Parameter
t
ACO1
t
AS1
t
AH
t
AWH
t
AWL
t
ACNT
f
ACNT
t
ACO1
t
AS1
t
AH
Notes:
3. C1 = 35 pF.
4. The f
values represent the highest frequency for pipeline data.
5. This parameter is measured with a 16-bit counter programmed into each LAB
6. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the t
AWH
and t
AWL
parameters must be swapped.
Description
7C342B-15
Min.
7C342B–20
Min.
Unit
ns
ns
ns
ns
ns
ns
MHz
Max.
15
Max.
20
Asynchronous Clock Input to Output Delay
[3]
Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input
[6]
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH Time
[6]
Asynchronous Clock Input LOW Time
[6]
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency
[5]
Asynchronous Clock Input to Output Delay
[3]
Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input
[5]
Input Hold Time from Asynchronous Clock Input
5
5
5
5
6
6
7
7
12
15
83.3
66.7
25
30
5
6
6
8
10
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C342B-25HC | 128-Macrocell MAX EPLDs |
| CY7C342B-25HI | 128-Macrocell MAX EPLDs |
| CY7C342B-25JC | 128-Macrocell MAX EPLDs |
| CY7C342B-25JI | 128-Macrocell MAX EPLDs |
| CY7C342B-25RC | 128-Macrocell MAX EPLDs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C342B-25HC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um Technology 5V 68-Pin Windowed LCC |
| CY7C342B-25HMB | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 128 Macro Cells 33.3MHz 0.8um (CMOS) Technology 5V |
| CY7C342B-25JC | 制造商: 功能描述: 制造商:Cypress Semiconductor 功能描述: 制造商:undefined 功能描述: |
| CY7C342B-25JI | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um (CMOS) Technology 5V 68-Pin PLCC |
| CY7C342B-25RMB | 制造商:Cypress Semiconductor 功能描述:128-MACROCELL MAX EPLD |
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