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參數(shù)資料
| 型號： | CY7C342B-20JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 128-Macrocell MAX EPLDs |
| 中文描述： | OT PLD, 33 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大小： | 350K |
| 代理商： | CY7C342B-20JI |
CY7C342B
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Document #: 38-03014 Rev. *B
Page 10 of 14
Switching Waveforms
(continued)
t
IN
t
ICS
t
RSU
t
RH
SYSTEM CLOCK
AT REGISTER
DATA FROM
LOGIC ARRAY
Internal Synchronous
SYSTEM CLOCK PIN
Ordering Information
Speed (ns)
15
Ordering Code
CY7C342B-15JC/JI
Package Name
J81
Package Type
Operating Range
Commercial/
Industrial
Commercial/
Industrial
Commercial/
Industrial
68-lead Plastic Leaded Chip Carrier
20
CY7C342B-20JC/JI
J81
68-lead Plastic Leaded Chip Carrier
25
CY7C342B-25HC/HI
CY7C342B-25JC/JI
CY7C342B-25RC/RI
CY7C342B-30JC/JI
H81
J81
R68
J81
68-pin Windowed Leaded Chip Carrier
68-lead Plastic Leaded Chip Carrier
68-pin Windowed Ceramic Pin Grid Array
68-lead Plastic Leaded Chip Carrier
30
Commercial/
Industrial
Commercial/
Industrial
35
CY7C342B-35JC/JI
CY7C342B-35RJ/RI
J81
R68
68-lead Plastic Leaded Chip Carrier
68-pin Windowed Ceramic Pin Grid Array
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C342B-25HC | 128-Macrocell MAX EPLDs |
| CY7C342B-25HI | 128-Macrocell MAX EPLDs |
| CY7C342B-25JC | 128-Macrocell MAX EPLDs |
| CY7C342B-25JI | 128-Macrocell MAX EPLDs |
| CY7C342B-25RC | 128-Macrocell MAX EPLDs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C342B-25HC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um Technology 5V 68-Pin Windowed LCC |
| CY7C342B-25HMB | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 128 Macro Cells 33.3MHz 0.8um (CMOS) Technology 5V |
| CY7C342B-25JC | 制造商: 功能描述: 制造商:Cypress Semiconductor 功能描述: 制造商:undefined 功能描述: |
| CY7C342B-25JI | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um (CMOS) Technology 5V 68-Pin PLCC |
| CY7C342B-25RMB | 制造商:Cypress Semiconductor 功能描述:128-MACROCELL MAX EPLD |
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