參數(shù)資料
型號(hào)： CY7C342B-20JI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： PLD
英文描述： 128-Macrocell MAX EPLDs
中文描述： OT PLD, 33 ns, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 4/14頁(yè)
文件大小： 350K
代理商： CY7C342B-20JI
CY7C342B
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Document #: 38-03014 Rev. *B
Page 4 of 14
Design Security
The CY7C342B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the entire
device.
The CY7C342B is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay t
EXP
to the overall delay. Similarly, there is an
additional t
PIA
delay for an input from an I/O pin when
compared to a signal from straight input pin.
When calculating synchronous frequencies, use t
SU
if all
inputs are on dedicated input pins. When expander logic is
used in the data path, add the appropriate maximum expander
delay, t
EXP
to t
S1
. Determine which of 1/(t
WH
+ t
WL
), 1/t
CO1
,
or 1/(t
EXP
+ t
S1
) is the lowest frequency. The lowest of these
frequencies is the maximum data path frequency for the
synchronous configuration.
When calculating external asynchronous frequencies, use
t
AS1
if all inputs are on the dedicated input pins.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
AS1
. Determine
which of 1/(t
AWH
+ t
AWL
), 1/t
ACO1
, or 1/(t
EXP
+ t
AS1
) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous config-
uration.
The parameter t
OH
indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If t
OH
is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
Typical I
CC
vs. f
MAX
400
300
200
100
1 kHz
10 kHz
100 kHz
1 MHz
I
C
MAXIMUM FREQUENCY
10 MHz
50 MHz
0
A
V
= 5.0V
Room Temp.
Output Drive Current
0
1
2
3
4
I
O
V
O
OUTPUTVOLTAGE (V)
250
200
150
100
50
5
I
OH
I
OL
V
CC
= 5.0V
Room Temp.
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