參數(shù)資料
型號(hào): CY7C342B-20JI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): PLD
英文描述: 128-Macrocell MAX EPLDs
中文描述: OT PLD, 33 ns, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 8/14頁(yè)
文件大?。?/td> 350K
代理商: CY7C342B-20JI
CY7C342B
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Document #: 38-03014 Rev. *B
Page 8 of 14
Commercial and Industrial Typical Internal Switching Characteristics
Over Operating Range (continued)
Parameter
t
COMB[9]
t
IC
t
ICS
t
FD
t
PRE
t
CLR
t
PIA
Description
7C342B-25
Min.
7C342B-30
Min.
7C342B-35
Min.
Unit
ns
ns
ns
ns
ns
ns
ns
Max.
3
14
3
1
5
5
14
Max.
4
16
2
1
6
6
16
Max.
4
16
1
2
7
7
20
Transparent Mode Delay
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Programmable Interconnect Array Delay Time
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
COMBINATORIAL
OUTPUT
t
PD1
/t
PD2
t
WL
t
SU
t
H
LOGIC ARRAY
t
WH
External Synchronous
CLOCK AT REGISTER
SYNCHRONOUS
SYNCHRONOUS
CLOCK PIN
DATA FROM
REGISTERED
OUTPUTS
t
CO1
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
AH
t
AS1
t
AWH
t
AWL
ASYNCHRONOUS
CLOCK INPUT
相關(guān)PDF資料
PDF描述
CY7C342B-25HC 128-Macrocell MAX EPLDs
CY7C342B-25HI 128-Macrocell MAX EPLDs
CY7C342B-25JC 128-Macrocell MAX EPLDs
CY7C342B-25JI 128-Macrocell MAX EPLDs
CY7C342B-25RC 128-Macrocell MAX EPLDs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C342B-25HC 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um Technology 5V 68-Pin Windowed LCC
CY7C342B-25HMB 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 128 Macro Cells 33.3MHz 0.8um (CMOS) Technology 5V
CY7C342B-25JC 制造商: 功能描述: 制造商:Cypress Semiconductor 功能描述: 制造商:undefined 功能描述:
CY7C342B-25JI 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um (CMOS) Technology 5V 68-Pin PLCC
CY7C342B-25RMB 制造商:Cypress Semiconductor 功能描述:128-MACROCELL MAX EPLD