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參數(shù)資料
| 型號(hào)： | CY7C342B-20JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 128-Macrocell MAX EPLDs |
| 中文描述： | OT PLD, 33 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 350K |
| 代理商： | CY7C342B-20JI |
CY7C342B
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Document #: 38-03014 Rev. *B
Page 7 of 14
t
AWH
t
AWL
t
ACNT
f
ACNT
Commercial and Industrial Typical Internal Switching Characteristics
Over Operating Range
Asynchronous Clock Input HIGH Time
[5]
Asynchronous Clock Input LOW Time
[5]
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency
[5]
11
9
14
11
16
14
20
25
50
40
33.3
Commercial and Industrial External Asynchronous Switching Characteristics
Over Operating Range (continued)
Parameter
Description
7C342B-15
Min.
7C342B–20
Min.
Unit
Max.
Max.
Parameter
t
IN
t
IO
t
EXP
t
LAD
t
LAC
t
OD
t
ZX[8]
t
XZ
t
RSU
t
RH
t
LATCH
t
RD
t
COMB[9]
t
IC
t
ICS
t
FD
t
PRE
t
CLR
t
PIA
t
IN
t
IO
t
EXP
t
LAD
t
LAC
t
OD
t
ZX[8]
t
XZ
t
RSU
t
RH
t
LATCH
t
RD
Notes:
7. C1 = 5 pF.
8. Sample tested only for an output change of 500 mV.
9. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial
operation.
Description
7C342B-15
Min.
7C342B-20
Min.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max.
3
3
8
8
5
3
5
5
Max.
4
4
10
12
5
3
5
5
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
[3]
Output Buffer Enable Delay
[3]
Output Buffer Disable Delay
[7]
Register Set-Up Time Relative to Clock Signal at Register
Register Hold Time Relative to Clock Signal at Register
Flow Through Latch Delay
Register Delay
Transparent Mode Delay
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Programmable Interconnect Array Delay Time
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
[3]
Output Buffer Enable Delay
[3]
Output Buffer Disable Delay
[7]
Register Set-Up Time Relative to Clock Signal at Register
Register Hold Time Relative to Clock Signal at Register
Flow Through Latch Delay
Register Delay
2
7
1
10
1
1
1
6
0
1
3
3
10
5
6
12
12
10
5
10
10
1
1
1
8
0
1
3
3
13
7
6
14
14
12
5
11
11
6
4
8
6
10
8
3
1
4
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C342B-25HC | 128-Macrocell MAX EPLDs |
| CY7C342B-25HI | 128-Macrocell MAX EPLDs |
| CY7C342B-25JC | 128-Macrocell MAX EPLDs |
| CY7C342B-25JI | 128-Macrocell MAX EPLDs |
| CY7C342B-25RC | 128-Macrocell MAX EPLDs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C342B-25HC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um Technology 5V 68-Pin Windowed LCC |
| CY7C342B-25HMB | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 128 Macro Cells 33.3MHz 0.8um (CMOS) Technology 5V |
| CY7C342B-25JC | 制造商: 功能描述: 制造商:Cypress Semiconductor 功能描述: 制造商:undefined 功能描述: |
| CY7C342B-25JI | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um (CMOS) Technology 5V 68-Pin PLCC |
| CY7C342B-25RMB | 制造商:Cypress Semiconductor 功能描述:128-MACROCELL MAX EPLD |
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