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參數(shù)資料
| 型號： | CY7C1380D |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM(18-Mb (512K x 36/1M x 18)管道式SRAM) |
| 中文描述： | 18兆位（為512k × 36/1M × 18）流水線的SRAM（18 - MB的（為512k × 36/1M × 18）管道式的SRAM） |
| 文件頁數(shù)： | 8/30頁 |
| 文件大小： | 554K |
| 代理商： | CY7C1380D |
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CY7C1380D
CY7C1382D
Document #: 38-05543 Rev. *D
Page 8 of 30
Because the CY7C1380D/CY7C1382D is a common I/O
device, the Output Enable (OE) must be deserted HIGH before
presenting data to the DQs inputs. Doing so will tri-state the
output drivers. As a safety precaution, DQs are automatically
tri-stated whenever a Write cycle is detected, regardless of the
state of OE.
Burst Sequences
The CY7C1380D/CY7C1382D provides a two-bit wraparound
counter, fed by A1: A0, that implements either an interleaved
or linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel Pentium applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
00
01
10
11
ZZ Mode Electrical Characteristics
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
[3, 4, 5, 6, 7, 8]
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
80
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
2t
CYC
2t
CYC
0
Operation
Add. Used
None
None
None
None
None
None
External
External
CE
1
H
L
L
L
L
X
L
L
CE
2
X
L
X
L
X
X
H
H
CE
3
X
X
H
X
H
X
L
L
ZZ
L
L
L
L
L
H
L
L
ADSP
X
L
L
H
H
X
L
L
ADSC
L
X
X
L
L
X
X
X
ADV
X
X
X
X
X
X
X
X
WRITE
X
X
X
X
X
X
X
X
OE CLK
X
X
X
X
X
X
L
H
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Q
Tri-State
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE
, CE
, and CE
are available only in the TQFP package. BGA package has only two chip selects CE
and CE
.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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