參數(shù)資料
型號: CY7C1380D
廠商: Cypress Semiconductor Corp.
英文描述: 18-Mbit (512K x 36/1M x 18) Pipelined SRAM(18-Mb (512K x 36/1M x 18)管道式SRAM)
中文描述: 18兆位(為512k × 36/1M × 18)流水線的SRAM(18 - MB的(為512k × 36/1M × 18)管道式的SRAM)
文件頁數(shù): 14/30頁
文件大?。?/td> 554K
代理商: CY7C1380D
CY7C1380D
CY7C1382D
Document #: 38-05543 Rev. *D
Page 14 of 30
3.3V TAP AC Test Conditions
Input pulse levels................................................ V
SS
to 3.3V
Input rise and fall times..................... ..............................1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels.................................................V
SS
to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
TDO
1.5V
20pF
Z = 50
50
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; V
DD
= 3.3V ±0.165V unless otherwise noted)
[12]
Parameter
Description
V
OH1
Output HIGH Voltage
Test Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
μA
I
OH
= –4.0 mA, V
DDQ
= 3.3V
I
OH
= –1.0 mA, V
DDQ
= 2.5V
I
OH
= –100 μA
V
OH2
Output HIGH Voltage
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
OL1
Output LOW Voltage
I
OL
= 8.0 mA
0.4
0.4
0.2
0.2
V
OL2
Output LOW Voltage
I
OL
= 100 μA
V
IH
Input HIGH Voltage
2.0
1.7
–0.3
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND < V
IN
< V
DDQ
Identification Register Definitions
Instruction Field
CY7C1380D
(512K x 36)
000
01011
101000
000000
100101
00000110100
1
CY7C1382D
(1 Mbit x 18)
000
01011
101000
000000
010101
00000110100
1
Description
Revision Number (31:29)
Device Depth (28:24)
[13]
Device Width (23:18) 119-BGA
Device Width (23:18) 165-FBGA
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Describes the version number.
Reserved for Internal Use
Defines memory type and architecture
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Notes:
12.All voltages referenced to V
SS
(GND).
13.Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
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CY7C1381D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
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