參數(shù)資料
型號: CY7C1380D
廠商: Cypress Semiconductor Corp.
英文描述: 18-Mbit (512K x 36/1M x 18) Pipelined SRAM(18-Mb (512K x 36/1M x 18)管道式SRAM)
中文描述: 18兆位(為512k × 36/1M × 18)流水線的SRAM(18 - MB的(為512k × 36/1M × 18)管道式的SRAM)
文件頁數(shù): 15/30頁
文件大?。?/td> 554K
代理商: CY7C1380D
CY7C1380D
CY7C1382D
Document #: 38-05543 Rev. *D
Page 15 of 30
Scan Register Sizes
Register Name
Bit Size (x36)
3
1
32
85
89
Bit Size (x18)
3
1
32
85
89
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM opera-
tions.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
相關(guān)PDF資料
PDF描述
CY7C1381D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100AXC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100AXI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100BGC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100BGI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
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