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參數(shù)資料
| 型號(hào)： | CY7C1380D |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM(18-Mb (512K x 36/1M x 18)管道式SRAM) |
| 中文描述： | 18兆位（為512k × 36/1M × 18）流水線的SRAM（18 - MB的（為512k × 36/1M × 18）管道式的SRAM） |
| 文件頁數(shù)： | 6/30頁 |
| 文件大?。?/td> | 554K |
| 代理商： | CY7C1380D |
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CY7C1380D
CY7C1382D
Document #: 38-05543 Rev. *D
Page 6 of 30
Pin Definitions
Name
I/O
Input-
Description
A
0
, A
1
, A
Synchronous
Address Inputs used to select one of the address locations
. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3 [2]
are sampled active. A1: A0
are fed to the two-bit counter..
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW
. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW
X
and BWE).
Byte Write Enable Input, active LOW
. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input
. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only
when a new external address is loaded.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3
to select/deselect the device. CE
2
is sampled only when a new external
address is loaded.
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
2
to select/deselect the device. CE
3
is sampled only when a new external address
is loaded.
Output Enable, asynchronous input, active LOW
. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW
. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW
. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW
. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ “Sleep” Input
. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
X
are placed in a tri-state condition.
Power Supply
Power supply inputs to the core of the device
.
Ground
Ground for the core of the device
.
I/O Ground
Ground for the I/O circuitry
.
I/O Power
Supply
Input-
Static
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
JTAG serial
output
Synchronous
packages.
BW
A
, BW
B
BW
C
, BW
D
GW
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Clock
Input-
Synchronous
BWE
CLK
CE
1
CE
2[2]
Input-
Synchronous
CE
3[2]
Input-
Synchronous
OE
Input-
Asynchronous
ADV
Input-
Synchronous
Input-
Synchronous
ADSP
ADSC
Input-
Synchronous
ZZ
Input-
Asynchronous
DQs, DQP
X
I/O-
Synchronous
V
DD
V
SS
V
SSQ
V
DDQ
Power supply for the I/O circuitry
.
MODE
Selects Burst Order
. When tied to GND selects linear burst sequence. When tied to V
DD
or left
TDO
Serial data-out to the JTAG circuit
. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP
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