參數(shù)資料
型號： CY7C1380D
廠商： Cypress Semiconductor Corp.
英文描述： 18-Mbit (512K x 36/1M x 18) Pipelined SRAM(18-Mb (512K x 36/1M x 18)管道式SRAM)
中文描述： 18兆位（為512k × 36/1M × 18）流水線的SRAM（18 - MB的（為512k × 36/1M × 18）管道式的SRAM）
文件頁數(shù)： 18/30頁
文件大?。?/td> 554K
代理商： CY7C1380D
CY7C1380D
CY7C1382D
Document #: 38-05543 Rev. *D
Page 18 of 30
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.3V to +4.6V
Supply Voltage on V
DDQ
Relative to GND ......–0.3V to +V
DD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage ...................................–0.5V to V
DD
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
DD
V
DDQ
3.3V
–5%/+10% 2.5V – 5%
to
V
DD
Electrical Characteristics
Over the Operating Range
[17, 18]
Parameter
V
DD
V
DDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
2.0
Max.
3.6
V
DD
2.625
Unit
V
V
V
V
V
V
V
V
V
V
V
μ
A
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O, I
OH
= –4.0 mA
for 2.5V I/O, I
OH
= –1.0 mA
for 3.3V I/O, I
OL
= 8.0 mA
for 2.5V I/O, I
OL
= 1.0 mA
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O
for 2.5V I/O
GND
≤
V
I
≤
V
DDQ
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
0.4
0.4
V
IH
Input HIGH Voltage
[17]
2.0
1.7
–0.3
–0.3
–5
V
DD
+ 0.3V
V
DD
+ 0.3V
0.8
0.7
5
V
IL
Input LOW Voltage
[17]
I
X
Input Leakage Current
except ZZ and MODE
Input Current of MODE Input = V
SS
–30
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
mA
mA
mA
mA
Input = V
DD
Input = V
SS
Input = V
DD
5
Input Current of ZZ
–5
30
5
350
300
275
160
150
140
70
I
OZ
I
DD
Output Leakage Current GND
≤
V
I
≤
V
DDQ,
Output Disabled
V
DD
Operating Supply
Current
f = f
MAX
= 1/t
CYC
–5
V
DD
= Max., I
OUT
= 0 mA,
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
I
SB1
Automatic CE
Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
f = f
MAX
= 1/t
CYC
I
SB2
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DDQ
– 0.3V,
f = 0
V
DD
= Max, Device Deselected, or
V
IN
≤
0.3V or V
IN
> V
DDQ
– 0.3V
f = f
MAX
= 1/t
CYC
I
SB3
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
135
130
125
80
mA
mA
mA
mA
I
SB4
Automatic CE
Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = 0
Notes:
17.Overshoot: V
(AC) < V
+1.5V (Pulse width less than t
/2), undershoot: V
(AC) > –2V (Pulse width less than t
CYC
/2).
18.TPower-up: Assumes a linear ramp from 0v to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
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