參數(shù)資料
型號(hào): CY7C1380D
廠(chǎng)商: Cypress Semiconductor Corp.
英文描述: 18-Mbit (512K x 36/1M x 18) Pipelined SRAM(18-Mb (512K x 36/1M x 18)管道式SRAM)
中文描述: 18兆位(為512k × 36/1M × 18)流水線(xiàn)的SRAM(18 - MB的(為512k × 36/1M × 18)管道式的SRAM)
文件頁(yè)數(shù): 30/30頁(yè)
文件大?。?/td> 554K
代理商: CY7C1380D
CY7C1380D
CY7C1382D
Document #: 38-05543 Rev. *D
Page 30 of 30
Document History Page
Document Title: CY7C1380D/CY7C1382D 18-Mbit (512K x 36/1M x 18)
Pipelined SRAM
Document Number: 38-05543
Orig. of
Change
**
254515
See ECN
RKF
*A
288531
See ECN
SYT
REV.
ECN NO. Issue Date
Description of Change
New data sheet
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 225MHz and 133 MHz Speed Bins
Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering Infor-
mation
Address expansion pins/balls in the pinouts for all packages are modified as per
JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000000 to 101000
Added separate row for 165 -FBGA Device Width (23:18)
Changed
Θ
JA
and
Θ
JC
for TQFP Package
from 31 and 6
°
C/W to 28.66 and 4.08
°
C/W respectively
Changed
Θ
JA
and
Θ
JC
for BGA Package
from 45 and 7
°
C/W to 23.8 and 6.2
°
C/W
respectively
Changed
Θ
JA
and
Θ
JC
for FBGA Package
from 46 and 3
°
C/W to 20.7 and 4.0
°
C/W
respectively
Modified V
OL,
V
OH
test conditions
Removed comment of ‘Lead-free BG packages availability’ below the Ordering
Information
Updated Ordering Information Table
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed the description of I
X
from Input Load Current to Input Leakage Current
on page# 18
Changed the I
X
current values of MODE on page # 18 from –5
μ
A and 30
μ
A
to –30
μ
A and 5
μ
A
Changed the I
X
current values of ZZ on page # 18 from –30
μ
A and 5
μ
A
to –5
μ
A and 30
μ
A
Changed V
IH
< V
DD
to V
IH
< V
DD
on page # 18
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND
Changed t
TH
, t
TL
from 25 ns to 20 ns and t
TDOV
from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
*B
326078
See ECN
PCI
*C
416321
See ECN
NXR
*D
475009
See ECN
VKN
相關(guān)PDF資料
PDF描述
CY7C1381D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100AXC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100AXI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-100BGC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
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