參數(shù)資料
型號(hào): CY7C1350F-166BGI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture
中文描述: 128K X 36 ZBT SRAM, 3.5 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
文件頁數(shù): 9/16頁
文件大?。?/td> 539K
代理商: CY7C1350F-166BGI
CY7C1350F
Document #: 38-05305 Rev. *A
Page 9 of 16
I
SB2
Automatic CE
Power-Down
Current—CMOS Inputs
Automatic CE
Power-Down
Current—CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
0.3V or V
IN
> V
DDQ
– 0.3V,
f = 0
V
DD
= Max, Device Deselected, or
V
IN
0.3V or V
IN
> V
DDQ
– 0.3V
f = f
MAX
= 1/t
CYC
All speeds
40
mA
I
SB3
4-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
All speeds
105
100
95
85
75
65
45
mA
mA
mA
mA
mA
mA
mA
I
SB4
Automatic CE
Power-Down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
, f = 0
AC Test Loads and Waveforms
Electrical Characteristics
Over the Operating Range
[10, 11]
(continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
OUTPUT
R = 317
R = 351
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
L
= 1.5V
3.3V
ALL INPUT PULSES
V
DD
GND
90%
10%
90%
10%
1 ns
1 ns
(c)
OUTPUT
R = 1667
R =1538
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
L
= 1.25V
2.5V
ALL INPUT PULSES
V
DD
GND
90%
10%
90%
10%
1 ns
1 ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
Thermal Resistance
[12]
Parameter
Θ
JA
Description
Test Conditions
TQFP
Package
41.83
BGA
Package
47.63
Units
°
C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard test methods
and procedures for measuring thermal imped-
ance, per EIA / JESD51.
Θ
JC
9.99
11.71
°
C/W
Capacitance
[12]
Parameter
Description
Test Conditions
TQFP
Package
BGA
Package
Unit
C
IN
C
I/O
Input Capacitance
T
A
= 25°C, f = 1 MHz,
V
DD
= 3.3V, V
DDQ
= 3.3V
5
5
pF
Input/Output Capacitance
5
7
pF
Note:
12.Tested initially and after any design or process changes that may affect these parameters.
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