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參數(shù)資料
| 型號： | CY7C1350F-166BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 539K |
| 代理商： | CY7C1350F-166BGI |
CY7C1350F
Document #: 38-05305 Rev. *A
Page 12 of 16
NOP, STALL, and DESELECT Cycles
[19, 20, 22]
ZZ Mode Timing
[23, 24]
Notes:
22.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
23.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
24.DQs are in high-Z when exiting ZZ sleep mode.
Switching Waveforms
(continued)
READ
Q(A3)
4
5
6
7
8
9
10
CLK
CE
WE
CEN
BW
[A:D]
ADV/LD
ADDRESS
A3
A4
A5
D(A4)
Data
In-Out (DQ)
A1
Q(A5)
WRITE
D(A4)
STALL
WRITE
D(A1)
1
2
3
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
t
CHZ
A2
D(A1)
Q(A2)
Q(A3)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
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PDF描述 |
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| CY7C1350F-200AC | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| CY7C1350F-200AI | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| CY7C1350F-200BGC | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| CY7C1350F-200BGI | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1350F-200AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP |
| CY7C1350F-200ACT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP T/R |
| CY7C1350F-250AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350G-100AXC | 制造商:MAJOR 功能描述: |
| CY7C1350G133AXC | 制造商:Cypress Semiconductor 功能描述: |
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