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參數(shù)資料
| 型號(hào)： | CY7C1350F-166BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大小： | 539K |
| 代理商： | CY7C1350F-166BGI |
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CY7C1350F
Document #: 38-05305 Rev. *A
Page 3 of 16
Pin Configuration
(continued)
2
A
3
A
4
5
A
6
A
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DQ
A
NC
V
DDQ
NC
NC
DQ
C
DQ
C
DQ
D
DQ
D
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
NC / 18M
V
DDQ
NC
NC
DQ
B
CE
2
A
DQP
C
A
A
V
DDQ
DQ
C
V
DDQ
NC
NC
DQ
C
DQ
C
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
DQ
D
NC
V
DD
A
NC / 72M
DQP
D
A
ADV/LD
V
DD
NC
A
A
CE
3
A
DQP
B
DQ
B
V
SS
V
SS
V
SS
BW
C
V
SS
V
SS
V
SS
BW
B
DQ
B
V
DDQ
DQ
B
DQ
B
DQ
A
DQP
A
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQ
A
NC
NC
NC
V
DDQ
NC
V
SS
V
SS
V
SS
BW
D
V
SS
V
SS
V
SS
MODE
CE
1
OE
NC / 9M
V
SS
V
SS
V
SS
BW
A
V
SS
V
SS
V
SS
NC
WE
V
DD
CLK
V
DDQ
NC
CEN
A1
A0
V
DDQ
DQ
A
ZZ
A
A
V
DD
A
NC / 36M
119-Ball Bump BGA
Pin Definitions
Name
119BGA
TQFP
I/O
Description
A0, A1, A
P4,N4,A2,
A3,A5,A6,
B3,B5,C2,
C3,C5,C6,
R2,R6,T3,
T4,T5
37,38,32,
33,34,35,
44,45,46,
47,48,49,
50,81,82,
99,10
Input-
Synchronous
Address Inputs used to select one of the 128K address locations
.
Sampled at the rising edge of the CLK. A
[1:0]
are fed to the two-bit burst
counter.
BW
[A:D]
L5,G5,
G3,L3
93,94,
95,96
Input-
Synchronous
Byte Write Inputs, active LOW
. Qualified with WE to conduct writes
to the SRAM. Sampled on the rising edge of CLK.
WE
H4
88
Input-
Synchronous
Write Enable Input, active LOW
. Sampled on the rising edge of CLK
if CEN is active LOW. This signal must be asserted LOW to initiate a
write sequence.
ADV/LD
B4
85
Input-
Synchronous
Advance/Load Input
. Used to advance the on-chip address counter
or load a new address. When HIGH (and CEN is asserted LOW) the
internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK
K4
89
Input-Clock
Clock Input
. Used to capture all synchronous inputs to the device. CLK
is qualified with CEN. CLK is only recognized if CEN is active LOW.
CE
1
E4
98
Input-
Synchronous
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK.
Used in conjunction with CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK.
Used in conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK.
Used in conjunction with CE
1
and
CE
2
to select/deselect the device.
CE
2
B2
97
Input-
Synchronous
CE
3
B6
92
Input-
Synchronous
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1350F-200AC | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| CY7C1350F-200AI | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| CY7C1350F-200BGC | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| CY7C1350F-200BGI | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1350F-200AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP |
| CY7C1350F-200ACT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP T/R |
| CY7C1350F-250AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350G-100AXC | 制造商:MAJOR 功能描述: |
| CY7C1350G133AXC | 制造商:Cypress Semiconductor 功能描述: |
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