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參數(shù)資料
| 型號(hào)： | CY7C1350F-166BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 539K |
| 代理商： | CY7C1350F-166BGI |
CY7C1350F
Document #: 38-05305 Rev. *A
Page 10 of 16
Switching Characteristics
Over the Operating Range
[17, 18]
250 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
1
1
1
1
225 MHz
200 MHz
166 MHz
133 MHz
100 MHz
Parameter
t
POWER
Description
V
DD
(typical) to the first
Access
[13]
1
1
ms
Clock
t
CYC
t
CH
t
CL
Output Times
t
CO
Clock Cycle Time
Clock HIGH
Clock LOW
4.0
1.7
1.7
4.4
2.0
2.0
5.0
2.0
2.0
6.0
2.5
2.5
7.5
3.0
3.0
10
3.5
3.5
ns
ns
ns
Data Output Valid After CLK
Rise
Data Output Hold After CLK
Rise
Clock to Low-Z
[14, 15, 16]
Clock to High-Z
[14, 15, 16]
2.6
2.6
2.8
3.5
4.0
4.5
ns
t
DOH
1.0
1.0
1.0
2.0
2.0
2.0
ns
t
CLZ
t
CHZ
t
OEV
t
OELZ
0
0
0
0
0
0
ns
ns
ns
ns
2.6
2.6
2.6
2.6
2.8
2.8
3.5
3.5
4.0
4.0
4.5
4.5
OE LOW to Output Valid
OE LOW to Output
Low-Z
[14, 15, 16]
0
0
0
0
0
0
t
OEHZ
OE HIGH to Output
High-Z
[14, 15, 16]
2.6
2.6
2.8
3.5
4.0
4.5
ns
Set-up Times
t
AS
Address Set-up Before CLK
Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
t
ALS
ADV/LD Set-up Before CLK
Rise
GW, BW
[A:D]
Set-Up Before
CLK Rise
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK
Rise
Chip Enable Set-Up Before
CLK Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
t
WES
0.8
1.2
1.2
1.5
1.5
1.5
ns
t
CENS
t
DS
0.8
0.8
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
t
CES
0.8
1.2
1.2
1.5
1.5
1.5
ns
Hold Times
t
AH
t
ALH
t
WEH
Address Hold After CLK Rise
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ADV/LD Hold after CLK Rise
GW, BW
[A:D]
Hold After CLK
Rise
t
CENH
t
DH
t
CEH
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK
Rise
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
Shaded areas contain advance information.
Notes:
13.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a Read or Write operation
can be initiated.
14.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
16.This parameter is sampled and not 100% tested.
17.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
18.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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| CY7C1350F-200AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP |
| CY7C1350F-200ACT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP T/R |
| CY7C1350F-250AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350G-100AXC | 制造商:MAJOR 功能描述: |
| CY7C1350G133AXC | 制造商:Cypress Semiconductor 功能描述: |
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