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參數(shù)資料
| 型號(hào)： | CY7C1350F-166BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 539K |
| 代理商： | CY7C1350F-166BGI |
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CY7C1350F
Document #: 38-05305 Rev. *A
Page 11 of 16
Switching Waveforms
Read/Write Timing
[19, 20, 21]
Notes:
19.For this waveform ZZ is tied LOW.
20.When CE is LOW, CE
is LOW, CE
is HIGH and CE
is LOW. When CE is HIGH, CE
is HIGH or CE
is LOW or CE
is HIGH.
21.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
WRITE
D(A1)
1
2
3
4
5
6
7
8
9
CLK
tCYC
t
CL
t
CH
10
CE
t
CEH
t
CES
WE
CEN
t
CENH
t
CENS
BW
[A:D]
ADV/LD
t
AH
t
AS
ADDRESS
A1
A2
A3
A4
A5
A6
A7
t
DH
t
DS
Data
In-Out (DQ)
t
CLZ
D(A1)
D(A2)
D(A5)
Q(A4)
Q(A3)
D(A2+1)
t
DOH
t
CHZ
t
CO
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
OE
t
OEV
t
OELZ
t
OEHZ
t
DOH
DON’T CARE
UNDEFINED
Q(A6)
Q(A4+1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1350F-200AC | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| CY7C1350F-200AI | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| CY7C1350F-200BGC | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| CY7C1350F-200BGI | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| CY7C1350F-225AI | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1350F-200AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP |
| CY7C1350F-200ACT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP T/R |
| CY7C1350F-250AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350G-100AXC | 制造商:MAJOR 功能描述: |
| CY7C1350G133AXC | 制造商:Cypress Semiconductor 功能描述: |
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