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參數(shù)資料
| 型號： | CY7C1350F-166BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 539K |
| 代理商： | CY7C1350F-166BGI |
CY7C1350F
Document #: 38-05305 Rev. *A
Page 4 of 16
OE
F4
86
Input-
Asynchronous
Output Enable, asynchronous input, active LOW
. Combined with
the synchronous logic block inside the device to control the direction of
the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data
pins. OE is masked during the data portion of a write sequence, during
the first clock when emerging from a deselected state, when the device
has been deselected.
CEN
M4
87
Input-
Synchronous
Clock Enable Input, active LOW
. When asserted LOW the Clock sig-
nal is recognized by the SRAM. When deasserted HIGH the Clock
signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
ZZ
T7
64
Input-
Asynchronous
ZZ “sleep” Input
. This active HIGH input places the device in a
non-time critical “sleep” condition with data integrity preserved. During
normal operation, this pin can be connected to Vss or left floating.
DQs
K6,K7,L6,
L7,M6,N6,
N7,P7,D7,
E6,E7,F6,
G6,G7,H6,
H7,D1,E1,
E2,F2,G1,
G2,H1,H2,
K1,K2,L1,
L2,M2,N1,
N2,P1
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,
7,8,9,12,
13,18,19,
22,23,23,
24,25,28,
29
I/O-
Synchronous
Bidirectional Data I/O Lines
. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, they
deliver the data contained in the memory location specified by the ad-
dress during the clock rise of the read cycle. The direction of the pins
is controlled by OE and the internal control logic. When OE is asserted
LOW, the pins can behave as outputs. When HIGH, DQ
s
and DQP
X
are
placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQP
[A:D]
P6,D6,
D2,P2
51,80,
1,30
I/O-
Synchronous
Bidirectional Data Parity I/O Lines
. Functionally, these signals are
identical to DQ
s
. During write sequences, DQP
[A:D]
is controlled by
BW
[A:D]
correspondingly.
Mode Input. Selects the burst order of the device.
When tied to GND selects linear burst sequence. When tied to V
DD
or
left floating selects interleaved burst sequence.
MODE
R3
31
Input
Strap pin
V
DD
C4,J2,
J4,J6,R4
15,16,41,
65,66,91
Power Supply
Power supply inputs to the core of the device
.
V
DDQ
A1,A7,F1,
F7,J1,J7,
M1,M7,U1,
U7
4,11,14,
20,27,54,
61,70
I/O Power
Supply
Power supply for the I/O circuitry
.
V
SS
D3,D5,E3,
E5,F3,F5
H3,H5,J3,
J5,K3,K5,
M3,M5,N3,
N5,P3,P5
5,10,17,2
1,26,40,5
5,60,67,
71,76,90
Ground
Ground for the device
.
NC
A4,B1,B7,
C1,C7,D4,
G4,L4,R1,
R5,R7,T1,
T2,T6,U6
38,39,42,
43,83,84
No Connects
. Not internally connected to the die.
9M, 18M, 36M, 72M, 144M and 288M are address expansion pins in
this device and will be used as address pins in their respective densi-
ties.
Pin Definitions
Name
119BGA
TQFP
I/O
Description
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|---|---|
| CY7C1350F-200AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP |
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| CY7C1350F-250AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350G-100AXC | 制造商:MAJOR 功能描述: |
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