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參數(shù)資料
| 型號： | CY7C1350F-166BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 539K |
| 代理商： | CY7C1350F-166BGI |
CY7C1350F
Document #: 38-05305 Rev. *A
Page 6 of 16
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE
ZZ
ADV/LD
WE
BW
x
X
OE
CEN
CLK
DQ
Deselect Cycle
None
H
L
L
X
X
L
L-H
Three-State
Continue
Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Three-State
Read Cycle
(Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle
(Continue Burst)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy Read
(Begin Burst)
External
L
L
L
H
X
H
L
L-H
Three-State
Dummy Read
(Continue Burst)
Next
X
L
H
X
X
H
L
L-H
Three-State
Write Cycle
(Begin Burst)
External
L
L
L
L
L
X
L
L-H
Data In (D)
Write Cycle
(Continue Burst)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
NOP/WRITE ABORT
(Begin Burst)
None
L
L
L
L
H
X
L
L-H
Three-State
WRITE ABORT
(Continue Burst)
Next
X
L
H
X
H
X
L
L-H
Three-State
IGNORE CLOCK EDGE
(Stall)
Current
X
L
X
X
X
X
H
L-H
—
SNOOZE MODE
None
X
H
X
X
X
X
X
X
Three-State
Notes:
2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for ALL Chip Enables active. BW
= 0 signifies at least one Byte Write Select is active, BW
x
=
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW
, and WE. See Write Cycle Descriptions table.
4. When a write cycle is detected, all DQs are three-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the DQs in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
[A:D]
= Three-state
when OE is inactive or when the device is deselected, and DQs and DQP
[A:D]
= data when OE is active.
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