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參數(shù)資料
| 型號(hào)： | CY7C1350F-166BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 539K |
| 代理商： | CY7C1350F-166BGI |
CY7C1350F
Document #: 38-05305 Rev. *A
Page 8 of 16
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
.....................................
65°C to +150°C
Ambient Temperature with
Power Applied
..................................................
55°C to +125°C
Supply Voltage on V
DD
Relative to GND
.........
0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State
..........................................
0.5V to V
DDQ
+ 0.5V
DC Input Voltage
.......................................
0.5V to V
DD
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Ambient
Temperature (T
A
)
0°C to +70°C
40°C to +85°C
V
DD
V
DDQ
2.5V - 5%
to V
DD
Com’l
3.3V - 5%/+10%
Ind’l
Electrical Characteristics
Over the Operating Range
[10, 11]
Parameter
V
DD
V
DDQ
V
OH
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Test Conditions
Min.
3.135
2.375
2.4
2.0
Max.
3.6
V
DD
Unit
V
V
V
V
V
V
V
V
V
V
μ
A
V
DDQ
= 3.3V, V
DD
= Min., I
OH
= –4.0 mA
V
DDQ
= 2.5V, V
DD
= Min., I
OH
= –1.0 mA
V
DDQ
= 3.3V, V
DD
= Min., I
OL
= 8.0 mA
V
DDQ
= 2.5V, V
DD
= Min., I
OL
= 1.0 mA
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
GND
≤
V
I
≤
V
DDQ
V
OL
Output LOW Voltage
0.4
0.4
V
IH
Input HIGH Voltage
[10]
2.0
1.7
–0.3
–0.3
5
V
DD
+ 0.3V
V
DD
+ 0.3V
0.8
0.7
5
V
IL
Input LOW Voltage
[10]
I
X
Input Load Current
except ZZ and MODE
Input Current of MODE
Input = V
SS
Input = V
DD
Input = V
SS
Input = V
DD
GND
≤
V
I
≤
V
DDQ,
Output Disabled
30
μ
A
μ
A
μ
A
μ
A
μ
A
5
Input Current of ZZ
5
30
5
I
OZ
Output Leakage
Current
V
DD
Operating Supply
Current
5
I
DD
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
4-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100MHz
4-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
325
290
265
240
225
205
120
115
110
100
90
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
SB1
Automatic CE
Power-Down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
f = f
MAX
= 1/t
CYC
Shaded areas contain advance information.
Notes:
10.Overshoot: V
(AC) < V
+1.5V (Pulse width less than t
/2), undershoot: V
(AC)> –2V (Pulse width less than t
CYC
/2).
11. T
Power-up
: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
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