參數(shù)資料
型號： CY7C1313BV18
廠商： Cypress Semiconductor Corp.
英文描述： 18-Mbit QDR-II SRAM 4-Word Burst Architecture(4字Burst結(jié)構(gòu),18-Mbit QDR-II SRAM)
中文描述： 18兆位QDR - II型SRAM的4字突發(fā)架構(gòu)（4字突發(fā)結(jié)構(gòu),18 - Mbit的QDR - II型的SRAM）
文件頁數(shù)： 10/28頁
文件大?。?/td> 459K
代理商： CY7C1313BV18
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document Number: 38-05620 Rev. *C
Page 10 of 28
Write Cycle Descriptions
(CY7C1311BV18 and CY7C1313BV18)
[2, 10]
BWS
0
/NWS
0
BWS
1
/NWS
1
L
K
K
Comments
L
L–H
–
During the Data portion of a Write sequence
:
CY7C1311BV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1313BV18
both bytes (D
[17:0]
) are written into the device.
L-H During the Data portion of a Write sequence
:
CY7C1311BV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1313BV18
both bytes (D
[17:0]
) are written into the device.
–
During the Data portion of a Write sequence
:
CY7C1311BV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1313BV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
L–H During the Data portion of a Write sequence
:
CY7C1311BV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will
remain unaltered,
CY7C1313BV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will
remain unaltered.
–
During the Data portion of a Write sequence
:
CY7C1311BV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1313BV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
L–H During the Data portion of a Write sequence
:
CY7C1311BV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1313BV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will
remain unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
H
H
L–H
–
Note:
10.Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
0
, NWS
1
, BWS
0
, BWS
1
, BWS
2
and BWS
3
can be altered on different
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
相關(guān)PDF資料
PDF描述
CY7C1315BV18 18-Mbit QDR-II SRAM 4-Word Burst Architecture(4字Burst結(jié)構(gòu),18-Mbit QDR-II SRAM)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1313BV18-167BZC 功能描述:靜態(tài)隨機存取存儲器 1Mx18 1.8V COM QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1313BV18-167BZCT 功能描述:靜態(tài)隨機存取存儲器 1Mx18 1.8V COM QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1313BV18-167BZXC 制造商:Cypress Semiconductor 功能描述:
CY7C1313BV18-200BZC 功能描述:靜態(tài)隨機存取存儲器 1Mx18 1.8V COM QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1313BV18-250BZC 功能描述:靜態(tài)隨機存取存儲器 1Mx18 1.8V COM QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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