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參數(shù)資料
| 型號： | CY28551LFXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK INTEL/AMD SIS VIA 64QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，AMD CPU |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:23 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
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CY28551
....................Document #: 001-05675 Rev. *C Page 17 of 28
CPU_STP# Clarification
The CPU_STP# signal is an active LOW input used for cleanly
stopping and starting the CPU outputs while the rest of the
clock generator continues to function. Note that the assertion
and deassertion of this signal is absolutely asynchronous.
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting of the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by 2 to 6
rising edges of the internal CPUC clock. The final state of the
stopped CPU clock is LOW due to tri-state; both CPUT and
CPUC outputs will not be driven.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner, synchronous manner meaning that no
short or stretched clock pulses will be produced when the
clock resumes. The maximum latency from the deassertion to
active outputs is between 2 and 6 CPU clock periods (2 clocks
are shown). If the control register tri-state bit corresponding to
the output of interest is programmed to '1', then the stopped
CPU outputs will be driven HIGH within 10 ns of CPU_Stop#
deassertion to a voltage greater than 200 mV.
PCI_STP# Clarification
The PCI_STP# signal is an active LOW input used for cleanly
stopping and starting the PCI and PCIEX outputs while the rest
of the clock generator continues to function. The PCIF and
PCIEX clocks are special in that they can be programmed to
ignore PCI_STP# by setting the register bit corresponding to
the output of interest to free running. Outputs set to free
running will ignore the PCI_STP# pin.
PCI_STP# Assertion
The impact of asserting the PCI_STP# signal is as follows. The
clock chip is to sample the PCI_STP# signal on a rising edge
of PCIF clock. After detecting the PCI_STP# assertion LOW,
all PCI and stoppable PCIF clocks will latch LOW on their next
HIGH-to-LOW transition. After the PCI clocks are latched
LOW, the stoppable PCIEX clocks will latch to LOW due to
tri-state, as shown in Figure 7. The one PCI clock latency
shown is critical to system functionality; any violation of this
may result in system failure. The Tsu_pci_stp# is the setup
time required by the clock generator to correctly sample the
PCI_STP# assertion. This time is 10 ns minimum.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal functions as follows.
The deassertion of the PCI_STP# signal is to be sampled on
the rising edge of the PCIF free running clock domain. After
detecting PCI_STP# deassertion, all PCI, stoppable PCIF and
stoppable PCIEX clocks will resume in a glitch-free manner.
The PCI and PCIEX clock resume latency should exactly
match the 1 PCI clock latency required for PCI_STP# entry.
The stoppable PCIEX clocks must be driven HIGH within
15 ns of PCI_STP# deassertion. Figure 8 shows the appro-
priate relationship. The Tsu_cpu_stp# is the setup time
required by the clock generator to correctly sample the
PCI_STP# deassertion. This time is 10 ns minimum.
CPU_STP#
CPUT
CPUC
Figure 5. CPU_STP# Assertion Timing Waveform
CP U _ S T P #
CP UT
CP UC
CP U T In t e r n a l
T d r iv e _ C P U _ S T P #, 10 n S > 200 m V
CP UC In t e r n a l
Figure 6. CPU_STP# Deassertion
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參數(shù)描述 |
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| CY2862-000 | 制造商:TE Connectivity 功能描述:82A0111-4-9-G110 |
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| CY28800OXC | 功能描述:時鐘緩沖器 PCI Express & Sata Diff Buffer 100MHz RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28800OXCT | 功能描述:時鐘緩沖器 PCI Express & Sata Diff Buffer 100MHz RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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