參數(shù)資料
型號(hào)： CY28551LFXCT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 23/28頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK INTEL/AMD SIS VIA 64QFN
標(biāo)準(zhǔn)包裝： 2,000
類(lèi)型： 時(shí)鐘/頻率發(fā)生器
PLL： 是
主要目的： Intel CPU，AMD CPU
輸入： 晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:23
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 400MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 帶卷 (TR)
CY28551
......................Document #: 001-05675 Rev. *C Page 4 of 28
Frequency Select Pins (FS[D:A])
To achieve host clock frequency selection, apply the appro-
priate logic levels to FS_A, FS_B, FS_C, and FS_D inputs
prior to VTT_PWRGD# assertion (as seen by the clock synthe-
sizer). When VTT_PWRGD# is sampled LOW by the clock
chip (indicating processor VTT voltage is stable), the clock
chip samples the FS_A, FS_B, FS_C, and FS_D input values.
For all logic levels of FS_A, FS_B, FS_C, FS_D, and FS_E,
VTT_PWRGD# employs a one-shot functionality, in that once
a valid LOW on VTT_PWRGD# has been sampled, all further
VTT_PWRGD#, FS_A, FS_B, FS_C, and FS_D transitions will
be ignored, except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3,
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 1. Frequency Select Table
FSD
FSC
FSB
FSA
Frequency Table (ROM)
FSEL3 FSEL2
FSEL1 FSEL0
CPU0
CPU1
SRC
LINK
PCI
CPU VCO
CPU PLL
Gear
Constant
(G)
CPU
M
CPU
N
PCIE
VCO
SRC PLL
Gear
Constant
PCIE
M
PCIE
N
0
266.6666667 266.6666667
100
66.6667
33.3333
800
80
60
200
800
30
60
200
0
1
133.3333333 133.3333333
100
66.6667
33.3333
800
40
60
200
800
30
60
200
0
1
0
200
100
66.6667
33.3333
800
60
200
800
30
60
200
0
1
166.6666667 166.6666667
100
66.6667
33.3333 666.6666667
60
63
175
800
30
60
200
0
1
0
333.3333333 333.3333333
100
66.6667
33.3333 666.6666667
120
63
175
800
30
60
200
0
1
0
1
100
66.6667
33.3333
800
30
60
200
800
30
60
200
0
1
0
400
100
66.6667
33.3333
800
120
60
200
800
30
60
200
0
1
200
250
100
66.6667
33.3333
1000
60
250
800
30
60
200
1
0
266.6666667 266.6666667
100 133.3333 33.3333
800
80
60
200
800
30
60
200
1
0
1
133.3333333 133.3333333
100 133.3333 33.3333
800
40
60
200
800
30
60
200
1
0
1
0
200
100 133.3333 33.3333
800
60
200
800
30
60
200
1
0
1
166.6666667 166.6666667
100 133.3333 33.3333 666.6666667
60
63
175
800
30
60
200
1
0
333.3333333 333.3333333
100 133.3333 33.3333 666.6666667
120
63
175
800
30
60
200
1
0
1
100
100 133.3333 33.3333
800
30
60
200
800
30
60
200
1
0
400
100 133.3333 33.3333
800
120
60
200
800
30
60
200
1
200
250
100 133.3333 33.3333
1000
60
250
800
30
60
200
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
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