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參數(shù)資料
| 型號： | CY28551LFXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK INTEL/AMD SIS VIA 64QFN |
| 標準包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，AMD CPU |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:23 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
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CY28551
......................Document #: 001-05675 Rev. *C Page 8 of 28
Byte 5: Control Register 5
Bit
@Pup
Type
Name
Description
7
0
R/W
CPU_SS1
CPU (PLL1) Spread Spectrum Selection
00: –0.5% (peak to peak)
01: ±0.25% (peak to peak)
10: –1.0% (peak to peak)
11: ±0.5% (peak to peak)
60
R/W
CPU_SS0
5
0
R/W
CPU_SS_OFF
PLL1 (CPUPLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
4
0
R/W
PCIE_SS0
PLL2 (PCIEPLL) Spread Spectrum Selection
0: –0.5% (peak to peak)
0: –1.0% (peak to peak)
3
0
R/W
PCIE_SS_OFF
PLL2 (PCIEPLL) Spread Spectrum Enable
0 = SRC spread off, 1 = SRC spread on
2
0
R/W
SATA_SS_OFF
PLL3 (SATAPLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
1
HW
R/W
SEL24_48
24M/48 MHz output selection
0 = 48 MHz, 1 = 24 MHz
0
1
R/W
Reserved
Byte 6: Control Register 6
Bit
@Pup
Type
Name
Description
7
0
R/W
SW_RESET
Software Reset.
When set, the device asserts a reset signal on SRESET# upon completion
of the block/word/byte write that set it. After asserting and deasserting the
SRESET# this bit will self clear (set to 0).
6
0
R/W
Reserved
5
0
R/W
FIX_LINK_PCI
LINK and PCI clock source selection
0 = PLL2(SRCPLL), 1 = PLL (SATAPLL)
4
HW
R
FSD
FSD Reflects the value of the FSD pin sampled on power up. 0 = FSD was
low during VTT_PWRGD# assertion.
3
HW
R
FSC
FSC Reflects the value of the FSC pin sampled on power up. 0 = FSC was
low during VTT_PWRGD# assertion.
2
HW
R
FSB
FSB Reflects the value of the FSB pin sampled on power up. 0 = FSB was
LOW during VTT_PWRGD# assertion
1
HW
R
FSA
FSA Reflects the value of the FSA pin sampled on power up. 0 = FSA was
LOW during VTT_PWRGD# assertion
0
HW
R
POWERGOOD
Power Status bit:
0 = Internal power or Internal resets are NOT valid
1 = Internal power and Internal resets are valid
Read only Bit 7 sets to 0 when Bit 7 = 0
Byte 7: Vendor ID
Bit
@Pup
Type
Name
Description
7
0
R
Revision Code Bit 3 Revision Code Bit 3
6
0
R
Revision Code Bit 2 Revision Code Bit 2
5
1
R
Revision Code Bit 1 Revision Code Bit 1
4
0
R
Revision Code Bit 0 Revision Code Bit 0
3
1
R
Vendor ID Bit 3
2
0
R
Vendor ID Bit 2
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| CY28800OXCT | 功能描述:時鐘緩沖器 PCI Express & Sata Diff Buffer 100MHz RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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