參數(shù)資料
型號： CY28551LFXCT
廠商： Silicon Laboratories Inc
文件頁數(shù)： 8/28頁
文件大小： 0K
描述： IC CLOCK INTEL/AMD SIS VIA 64QFN
標(biāo)準(zhǔn)包裝： 2,000
類型： 時鐘/頻率發(fā)生器
PLL： 是
主要目的： Intel CPU，AMD CPU
輸入： 晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:23
差分 - 輸入:輸出： 無/是
頻率 - 最大： 400MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 帶卷 (TR)
CY28551
....................Document #: 001-05675 Rev. *C Page 16 of 28
driven to a LOW value and held prior to turning off the VCOs
and the crystal oscillator
PD Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs must be held LOW on their
next HIGH-to-LOW transition and differential clocks must be
held HIGH or tri-stated (depending on the state of the control
register drive mode bit) on the next “Diff clock#” HIGH-to-LOW
transition within 4 clock periods. When the SMBus PD drive
mode bit corresponding to the differential (CPU, SRC, and
DOT) clock output of interest is programmed to '0', the clock
output must be held with “Diff clock” pin driven HIGH at 2 x Iref,
and “Diff clock#” tri-state. If the control register PD drive mode
bit corresponding to the output of interest is programmed to ‘1’,
then both the “Diff clock” and the “Diff clock#” are tri-state. Note
Figure 3 shows CPUT = 133 MHz and PD drive mode = '1' for
all differential outputs. This diagram and description is appli-
cable to valid CPU frequencies 100, 133, 166, and 200 MHz.
In the event that PD mode is desired as the initial power-on
state, PD must be asserted HIGH in less than 10
s after
asserting VTT_PWRGD#.
PD Deassertion
The power-up latency must be less than 1.8 ms. This is the
time from the deassertion of the PD pin or the ramping of the
power supply until the time that stable clocks are output from
the clock chip. All differential outputs stopped in a tri-state
condition resulting from power down must be driven HIGH in
less than 300
s of PD deassertion to a voltage greater than
200 mV. After the clock chip's internal PLL is powered up and
locked, all outputs are to be enabled within a few clock cycles
of each other. Figure 4 is an example showing the relationship
of clocks coming up. Unfortunately, we can not show all
possible combinations; designers need to ensure that from the
first active clock output to the last takes no more than two full
PCI clock cycles.
D O T 96C
PD
C P U C , 133 M H z
C P U T , 133 M H z
S R C C 100 M H z
U SB, 4 8 M H z
DO T 9 6 T
S R C T 100 M H z
PC I , 3 3 M H z
RE F
LI N K
Figure 3. PD Assertion Timing Waveform
D O T 96C
PD
CP UC , 1 3 3 M Hz
CP UT , 1 3 3 M Hz
S R CC 1 0 0 M Hz
US B , 4 8 M H z
D O T 96T
SR C T 1 0 0 M H z
Ts t a b le
<1. 8 m s
P C I, 3 3 M H z
RE F
T d r iv e _ P W RDN #
<3 0 0
s > 2 0 0 m V
LI N K
Figure 4. PD Deassertion Timing Waveform
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