參數(shù)資料
型號: CY28551LFXCT
廠商: Silicon Laboratories Inc
文件頁數(shù): 2/28頁
文件大?。?/td> 0K
描述: IC CLOCK INTEL/AMD SIS VIA 64QFN
標(biāo)準(zhǔn)包裝: 2,000
類型: 時鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU,AMD CPU
輸入: 晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:23
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-QFN(9x9)
包裝: 帶卷 (TR)
CY28551
....................Document #: 001-05675 Rev. *C Page 10 of 28
Byte 10: Control Register 10
Bit
@Pup
Type
Name
Description
7
0
R/W
DF1_N7
The DF1_N[8:0] configures CPU frequency for Dynamic Frequency.
DOC[1:2] =01.
60
R/W
DF1_N6
50
R/W
DF1_N5
40
R/W
DF1_N4
30
R/W
DF1_N3
20
R/W
DF1_N2
10
R/W
DF1_N1
00
R/W
DF1_N0
Byte 11: Control Register 11
Bit
@Pup
Type
Name
Description
7
0
R/W
DF2_N7
The DF2_N[8:0] configures CPU frequency for Dynamic Frequency.
DOC[1:2] =10
60
R/W
DF2_N6
50
R/W
DF2_N5
40
R/W
DF2_N4
30
R/W
DF2_N3
20
R/W
DF2_N2
10
R/W
DF2_N1
00
R/W
DF2_N0
Byte 12: Control Register 12
Bit
@Pup
Type
Name
Description
7
0
R/W
DF3_N7
The DF3_N[8:0] configures CPU frequency for Dynamic Frequency.
DOC[1:2] =11
6
0
R/W
DF3_N6
5
0
R/W
DF3_N5
4
0
R/W
DF3_N4
3
0
R/W
DF3_N3
2
0
R/W
DF3_N2
1
0
R/W
DF3_N1
0
R/W
DF3_N0
Byte 13: Control Register 13
Bit
@Pup
Type
Name
Description
7
0
R/W
Recovery_Frequency This bit allows selection of the frequency setting to which the clock will be
restored once the system is rebooted
0 = Use HW settings 1 = Recovery N[8:0]
6
0
R/W
Timer_SEL
Timer_SEL selects the WD reset function at SRESET pin when WD times
out.
0 = Reset and Reload Recovery_Frequency
1 = Only Reset
5
1
R/W
Time_Scale
Time_Scale allows selection of WD time scale
0 = 294 ms, 1 = 2.34 s
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