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參數(shù)資料
| 型號(hào)： | CY28551LFXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 6/28頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK INTEL/AMD SIS VIA 64QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，AMD CPU |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:23 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
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CY28551
....................Document #: 001-05675 Rev. *C Page 14 of 28
Dynamic Frequency
Dynamic Frequency – Dynamic Frequency (DF) is a technique
used to increase CPU frequency or SRC frequency dynami-
cally from any starting value. The user selects the starting
point, either by HW, FSEL, or DAF, then enables DF. After that,
DF will dynamically change as determined by DF-N registers
and the M value of frequency table.
DF Pin – There are two pins to be used on Dynamic Frequency
(DF). When used as DF, these two pins will map to four DF-N
registers that correspond to different “N” values for Dynamic
Frequency. Any time there is a change in DF, it should load the
new value.
DF_EN bit – This bit enables the DF mode. By default, it is not
set. When set, the operating frequency is determined by
DF[2:0] pins. Default = 0, (No DF)
Dial-A-Frequency (CPU & PCIEX)
This feature allows users to overclock their systems by slowly
stepping up the CPU or SRC frequency. When the program-
mable output frequency feature is enabled, the CPU and SRC
frequencies are determined by the following equation:
Fcpu = G * N/M or Fcpu = G2 * N, where G2 = G/M.
‘N’ and ‘M’ are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively. ‘G’ stands for the PLL Gear Constant, which is
determined by the programmed value of FS[E:A]. See Table 1
for the Gear Constant for each Frequency selection. The PCI
Express only allows user control of the N register; the M value
is fixed and documented in Table 1.
In this mode, the user writes the desired N and M value into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value if required.
Associated Register Bits
CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note: The CPU_DAF_N and M register must contain
valid values before CPU_DAF is set. Default = 0, (No DAF).
CPU_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
frequency select table (Table 1).
CPU_DAF_M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0. The allowable values for M are detailed in the frequency
select table (Table 1).
SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note: The SRC_DAF_N register must contain valid
values before SRC_DAF is set. Default = 0, (No DAF).
SRC_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
frequency select table (Table 1).
Recovery – The recovery mechanism during CPU DAF, when
the system locks up and the watchdog timer is enabled, is
determined
by
the
“Watchdog
Recovery
Mode”
and
“Watchdog Autorecovery Enable” bits. The possible recovery
methods are: (A) Auto, (B) Manual (by Recovery N), (C) HW,
and (D) No recovery, just send reset signal.
There is no recovery mode for SRC Dial-a-Frequency.
Software Frequency Select
This mode allows the user to select the CPU output
frequencies using the Software Frequency select bits in the
SMBUS register.
FSEL – There are four bits (for 16 combinations) to select
predetermined CPU frequencies from a table. The table selec-
tions are detailed in Table 1.
FS_Override – This bit allows the CPU frequency to be
selected from HW or FSEL settings. By default, this bit is not
set and the CPU frequency is selected by HW. When this bit
is set, the CPU frequency is selected by the FSEL bits. Default
= 0.
Recovery – The recovery mechanism during FSEL when the
system locks up is determined by the “Watchdog Recovery
Mode” and “Watchdog Autorecovery Enable” bits. The only
possible recovery method is to use Hardware Settings. Auto
recovery or manual recovery can cause a wrong output
frequency because the output divider may have changed with
the selected CPU frequency and these recovery methods will
not recover the original output divider setting.
Smooth Switching
The device contains one smooth switch circuit, which is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667
s. The frequency
overshoot and undershoot will be less than 2%.
The smooth switch circuit can be assigned auto or manual
mode. In auto mode, the clock generator will assign smooth
switch automatically when the PLL will perform overclocking.
For manual mode, the smooth switch circuit can be assigned
to either PLL via SMBUS. By default the smooth switch circuit
is set to auto mode. Either PLL can still be overclocked when
it does not have control of the smooth switch circuit, but it is
not guaranteed to transition to the new frequency without large
frequency glitches.
Do not enable overclocking and change the N values of both
PLLs in the same SMBUS block write and use smooth switch
mechanism on spread spectrum on/off.
DOC[2:1]
DOC N register
00
Original Frequency
01
DF1_N
10
DF2_N
11
DF3_N
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