參數(shù)資料
型號: CY28551LFXCT
廠商: Silicon Laboratories Inc
文件頁數(shù): 1/28頁
文件大?。?/td> 0K
描述: IC CLOCK INTEL/AMD SIS VIA 64QFN
標(biāo)準(zhǔn)包裝: 2,000
類型: 時鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU,AMD CPU
輸入: 晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:23
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-QFN(9x9)
包裝: 帶卷 (TR)
Universal Clock Generator for Intel, VIA, and SIS
CY28551
...................... Document #: 001-05675 Rev. *C Page 1 of 28
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
Features
Compliant to Intel CK505
Selectable CPU clock buffer type for Intel P4 or K8
selection
Selectable CPU frequencies
Universal clock to support Intel, SiS and VIA platform
0.7V Differential CPU clock for Intel CPU
3.3V Differential CPU clock for AMD K8
100 MHz differential SRC clocks
96 MHz differential dot clock
133 MHz Link clock
48 MHz USB clock
33 MHz PCI clocks
Dynamic Frequency Control
Dial-A-Frequency
WatchDog Timer
Two Independent Overclocking PLLs
Low-voltage frequency select input
I2C support with readback capabilities
Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
3.3V Power supply
64-pin QFN package
CPU
SRC
SATA
PCI
REF
LINK
DOT96
24_48M
48M
x 2
x 8
x1
x 7
x 3
x2
x 1
x1
x 1
P
C
I5/*S
E
L0
P
C
I4/*S
E
LP
4_K
8
V
D
DP
CI
PC
3
/*
F
SB
P
C
I2/**
F
SA
VSS
PC
I
P
C
I1/C
L
K
REQ#A
P
C
I0/C
L
K
REQ#B
**
DO
C1
R
E
S
E
T
_
I#
/SR
ES
ET
#
R
E
F0
/**
FS
D
RE
F
1
/**
F
S
C
RE
F
2
/**
M
O
D
E
VSS
R
E
F
XI
N
XO
U
T
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PCI6_F 1
48 VDDREF
VDD48 247 SCLK
**SEL24_48 / 24_48M 3
46 SDATA
**SEL1/48M 4
45 VTTPWRG#/PD
VSS48 5
44 CPUT0
VDDDOT 6
43 CPUC0
LINK0/DOT96T/SATAT 7
42 VDDCPU
LINK1/DOT96C/SATAC 8
41 CPUT1
VSSDOT 9
40 CPUC1
VDDSATA 10
39 VSSCPU
SATAT/PCIEXT0 11
38 **DOC2
SATAC/PCIEXC0 12
37 VSSA
VSSSATA 13
36 VDDA
PCIEXT1 14
35 PCIEXT8/CPU_STP#
PCIEXC1 15
34 PCIEXC8/PCI_STP#
VSSPCIE 16
33 VDDPCIE
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PCIE
XT2
PC
IE
XC
2
VDD
P
CIE
PCIE
XT3
PC
IE
XC
3
VS
SP
CIE
PCIE
XT4
PC
IE
XC
4
VDD
P
CIE
PC
IE
XC
5
PCIE
XT5
PC
IE
XC
6
PCIE
XT6
VS
SP
CIE
PC
IE
XC
7
PCIE
XT7
CY28551
Block Diagram
Pin Configuration
* Indicates internal pull up
** indicates internal pull down
VDD_REF
VDD_CPU
VDD_PCIEX
TPWR_GD#/PD
PLLReference
FS[D:A]
PLL1
CPU
VDD_DOT
PLL3
SATA
Divider
PLL4
Fixed
Divider
REF[2:0]
CPUT[1:0]
CPUC[1:0]
PCIET[8:1]
PCIEC[8:1]
DOT96T/SATAT/LINK0
DOT96C/SATAC/LINK1
I2C
Logic
SDATA
SCLK
14.318MHz
Crystal
Xin
Xout
VDD_48
48M
VDD_PCI
PCI[6:0]
DOC[2:1]
PLL2
PCIEX
VDD_SATA
PCIET0/SATAT
PCIEC0/SATAC
WDT
SRESET#
24_48M
SEL[1:0]
SEL_P4_K8
SEL24_48
Multiplexer
Controller
Divider
RESET_I#
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