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參數(shù)資料
| 型號： | CY28346 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Clock Synthesizer with Differential CPU Outputs |
| 中文描述： | 時鐘合成器的差分輸出的CPU |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 179K |
| 代理商： | CY28346 |
CY28346
Document #: 38-07331 Rev. *B
Page 6 of 20
Dial-a-Frequency Features
SMBus Dial-a-Frequency feature is available in this device via
Byte8 and Byte9.
P is a large-value PLL constant that depends on the frequency
selection achieved through the hardware selectors (S1, S0). P
value may be determined from
Table 2
.
Dial-a-dB Features
SMBus Dial-a-dB feature is available in this device via Byte8
and Byte9.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to
minimizing EMI radiation generated by repetitive digital
signals. A clock presents the greatest EMI energy at the center
frequency it is generating. Spread Spectrum distributes this
energy over a specific and controlled frequency bandwidth
therefore causing the average energy at
any one point in this band to decrease in value. This technique
is achieved by modulating the clock away from its resting
frequency by a certain percentage (which also determines the
amount of EMI reduction). In this device, Spread Spectrum is
enabled by setting specific register bits in the SMBus control
bytes.
Table 3
is a listing of the modes and percentages of
Spread Spectrum modulation that this device incorporates.
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
Table 2. P Value
S(1:0)
0 0
0 1
1 0
1 1
P
32005333
48008000
96016000
64010667
Table 3. Spread Spectrum
SS2
0
0
0
0
1
1
1
1
SS1
0
0
1
1
0
0
1
1
SS0
0
1
0
1
0
1
0
1
Spread Mode
Down
Down
Down
Down
Center
Center
Center
Center
Spread%
+0.00,
–
0.25
+0.00,
–
0.50
+0.00,
–
0.75
+0.00,
–
1.00
+0.13,
–
0.13
+0.25,
–
0.25
+0.37,
–
0.37
+0.50,
–
1.50
Measurement Point
2pF
CPUT
MULTSEL
T
PCB
T
PCB
CPUC
220
63.4
63.4
475
33.2
33.2
Measurement Point
2pF
Figure 1. 1.0V Test Load Termination
CPUT
MULTSEL
T
PCB
T
PCB
CPUC
33
33
Measurement Point
49.9
49.9
2pF
Measurement Point
2pF
475
VDD
Figure 2. 0.7V Test Load Termination
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