參數(shù)資料
型號(hào)： CY28346
廠商： Cypress Semiconductor Corp.
英文描述： Clock Synthesizer with Differential CPU Outputs
中文描述： 時(shí)鐘合成器的差分輸出的CPU
文件頁(yè)數(shù)： 11/20頁(yè)
文件大?。?/td> 179K
代理商： CY28346
CY28346
Document #: 38-07331 Rev. *B
Page 11 of 20
PCI_STP#
–
Deassertion (transition from logic
“
0
”
to logic
“
1
”
)
The deassertion of the PCI_STP# signal will cause all PCI(0:6)
and stoppable PCI_F(0:2) clocks to resume running in a
synchronous manner within two PCI clock periods after
PCI_STP# transitions to a HIGH level.
Note
. The PCI STOP function is controlled by two inputs. One
is the device PCI_STP# pin number 34 and the other is SMBus
Byte 0,Bit 3. These two inputs to the function are logically
AND
’
ed. If either the external pin or the internal SMBus
register bit is set LOW, the stoppable PCI clocks will be
stopped in a logic LOW state. Reading SMBus Byte 0,Bit 3 will
return a 0 value if either of these control bits are set LOW
(which indicates that the devices stoppable PCI clocks are not
running).
PD# (Power-down) Clarification
The PD# (power-down) pin is used to shut off all clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO and PLLs are also powered down. All clocks are
shut down in a synchronous manner so has not to cause
glitches while transitioning to the LOW
“
stopped
”
state.
PD#
–
Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock, then on the next HIGH-to-LOW transition
of PCIF, the PCIF clock is stopped LOW. On the next
HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped
LOW. From this time, each clock will stop LOW on its next
HIGH-to-LOW transition, except the CPUT clock. The CPU
clocks are held with the CPUT clock pin driven HIGH with a
value of 2
×
Iref, and CPUC undriven. After the last clock has
stopped, the rest of the generator will be shut down.
PD#
–
Deassertion
The power-up latency between PD# rising to a valid logic
‘
1
’
level and the starting of all clocks is less than 3.0 ms.
PCI_STP#
PCI_F(0:2) 33M
PCI(0:6) 33M
setup
t
Figure 11. PCI_STP# Assertion Waveform
PCI_STP#
PCI_F(0:2)
PCI(0:6)
setup
t
Figure 12. PCI_STP# Deassertion Waveform
相關(guān)PDF資料
PDF描述
CY28346OC CONN BNC PLUG CRIMP RG-TFE-59,62
CY28346OCT CONN BNC PLUG CRIMP RG-59,62
CY28346ZC Clock Synthesizer with Differential CPU Outputs
CY28346ZCT Clock Synthesizer with Differential CPU Outputs
CY28347 HDC-HA-48-SVL1/29 RoHS Compliant: Yes
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CY28346-2 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Clock Synthesizer with Differential CPU Outputs
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CY28346OCT 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Clock Synthesizer with Differential CPU Outputs
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