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參數(shù)資料
| 型號： | CY28346 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Clock Synthesizer with Differential CPU Outputs |
| 中文描述： | 時鐘合成器的差分輸出的CPU |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 179K |
| 代理商： | CY28346 |
CY28346
Document #: 38-07331 Rev. *B
Page 14 of 20
Maximum Ratings
[5]
Input Voltage Relative to V
SS
:.............................. V
SS
–
0.3V
Input Voltage Relative to V
DDQ
or AV
DD
: .............V
DD
+ 0.3V
Current Accuracy
[6]
Storage Temperature:................................
–
65
°
C to + 150
°
C
Operating Temperature:.................................... 0
°
C to +85
°
C
Maximum Power Supply:................................................3.5V
Parameter
Iout
Conditions
Configuration
Load
Min.
–
7%
Inom
–
12%
Inom
Max.
+ 7%
Inom
+ 12%
Inom
V
DD
= nominal (3.30V)
M0 = 0 or 1 and Rr (see
Table 1
)
Nominal test load for given
configuration
Nominal test load for given
configuration
Iout
V
DD
= 3.30 ± 5%
All combinations of M0 or 1 and Rr
(see
Table 1
)
DC Parameters
(VDD = VDDA = 3.3V ±5%, TA = 0
°
C to +70
°
C)
Parameter
I
DD
3.3V
I
PD
3.3V
C
IN
C
OUT
L
PIN
C
XTAL
Description
Conditions
Min.
Typ.
Max.
280
Note 8
5
6
7
42
Unit
mA
mA
pF
pF
nH
pF
Dynamic Supply Current
Power-down Supply Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Crystal Pin Capacitance
All frequencies at maximum values
[7]
PD# asserted
Measured from the X
IN
or X
OUT
pin to ground
30
36
AC Parameters
(V
DD
= V
DDA
= 3.3V ±5%, T
A
= 0
°
C to +70
°
C)
Parameter
Crystal
T
DC
T
PERIOD
Description
66 MHz
Min.
100 MHz
Min.
133 MHz
Min.
200 MHz
Min.
Unit
Notes
Max.
Max.
Max.
Max.
X
IN
Duty Cycle
X
IN
period
47.5
69.84
52.5
71.0
47.5
69.84
52.5
71.0
47.5
69.84
52.5
71.0
47.5
69.84
52.5
71.0
%
ns
9, 10, 11
9, 12,
13, 10
V
HIGH
V
LOW
T
R
/ T
F
T
CCJ
X
IN
HIGH Voltage
X
IN
LOW Voltage
X
IN
Rise and Fall Times
X
IN
Cycle to Cycle Jitter
0.7V
DD
0
V
DD
0.3V
DD
10.0
500
0.7V
DD
0
V
DD
0.3V
DD
10.0
500
0.7V
DD
0
V
DD
0.3V
DD
10.0
500
0.7V
DD
0
V
DD
0.3V
DD
10.0
500
V
V
ns
ps
14
12, 15,
10
CPU at 0.7V Timing
T
DC
CPUT and CPUC Duty
Cycle
CPUT and CPUC
Period
Any CPU to CPU Clock
Skew
45
55
45
55
45
55
45
55
%
15, 16,
19
15, 16,
19
12, 15,
16
T
PERIOD
14.85
15.3
9.85
10.2
7.35
7.65
4.85
5.1
ns
T
SKEW
100
100
100
100
ps
Notes:
5.
6.
7.
8.
9.
10. This parameter is measured as an average over 1
11.
This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
12. All outputs loaded as per
Table 9
below.
13. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).
14. Measured between 0.2V
and 0.7V
.
15. This measurement is applicable with Spread ON or Spread OFF.
16. Measured at crossing point (Vx) or where subtraction of CLK
–
CLK# crosses 0V Measured from V
OL
= 0.175V to V
OH
= 0.525V.
17. Measured from V
= 0.175V to V
OH
= 0.525V.
18. Determined as a fraction of 2*(Trise
–
Tfall)/ (Trise+Tfall).
19. Test load is Rta = 33.2
, Rd = 49.9
.
Multiple Supplies:
The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Inom refers to the expected current based on the configuration of the device.
All outputs loaded as per maximum capacitive load table.
Absolute value = ((Programmed CPU Iref)
×
(2)) + 10 mA.
μ
s duration, with a crystal center frequency of 14.31818 MHz.
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