- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379006 > CY28346 (Cypress Semiconductor Corp.) Clock Synthesizer with Differential CPU Outputs PDF資料下載
參數(shù)資料
| 型號： | CY28346 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Clock Synthesizer with Differential CPU Outputs |
| 中文描述： | 時鐘合成器的差分輸出的CPU |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 179K |
| 代理商： | CY28346 |
CY28346
Document #: 38-07331 Rev. *B
Page 4 of 20
Byte 2: PCI Clock Control Register
(all bits are Read and Write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
1
1
1
1
1
Pin#
53
18
17
16
13
12
11
10
Description
REF Output Control. 0 = high strength, 1 = low strength.
PCI6 Output Control. 1 = enabled, 0 = forced LOW.
PCI5 Output Control. 1 = enabled, 0 = forced LOW.
PCI4 Output Control. 1 = enabled, 0 = forced LOW.
PCI3 Output Control. 1 = enabled, 0 = forced LOW.
PCI2 Output Control. 1 = enabled, 0 = forced LOW.
PCI1 Output Control. 1 = enabled, 0 = forced LOW.
PCI0 Output Control. 1 = enabled, 0 = forced LOW.
Byte 3: PCI_F Clock and 48M Control Register
(all bits are Read and Write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
0
0
0
1
1
1
Pin#
38
39
7
6
5
7
6
5
Description
48MDOT Output Control. 1 = enabled, 0 = forced LOW.
48MUSB Output Control. 1 = enabled, 0 = forced LOW.
PCI_STP#, Control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
PCI_STP#, Control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
PCI_STP#, Control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.
PCI_F2 Output Control. 1 = running, 0 = forced LOW.
PCI_F1 Output Control. 1 = running, 0 = forced LOW.
PCI_F0 Output Control. 1 = running, 0 = forced LOW.
Byte 4: DRCG Control Register
(all bits are Read and Write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
1
1
1
1
1
1
Pin#
Description
SS2 Spread Spectrum Control Bit (0 = down spread, 1 = center spread).
Reserved. Set = 0.
3V66_0 Output Enabled. 1 = enabled, 0 = disable.
3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled.
3V66_5 Output Enable. 1 = enabled, 0 = disabled.
66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled.
66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled.
66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled.
33
35
24
23
22
21
Byte 5: Clock Control Register
(all bits are Read and Write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
0
0
0
0
0
0
Pin#
Description
SS1 Spread Spectrum Control Bit.
SS0 Spread Spectrum Control Bit.
66IN to 66M delay Control MSB.
66IN to 66M delay Control LSB.
Reserved. Set = 0.
48MDOT Edge Rate Control. When set to 1, the edge is slowed by 15%.
Reserved. Set = 0.
USB edge rate control. When set to 1, the edge is slowed by 15%.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28346OC | CONN BNC PLUG CRIMP RG-TFE-59,62 |
| CY28346OCT | CONN BNC PLUG CRIMP RG-59,62 |
| CY28346ZC | Clock Synthesizer with Differential CPU Outputs |
| CY28346ZCT | Clock Synthesizer with Differential CPU Outputs |
| CY28347 | HDC-HA-48-SVL1/29 RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28346_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential CPU Outputs |
| CY28346-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential CPU Outputs |
| CY28346-2_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential CPU Outputs |
| CY28346OC | 制造商:Rochester Electronics LLC 功能描述:FTG FOR INTEL 830M AND 845 CHIPSETS (CK-408) - Bulk |
| CY28346OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential CPU Outputs |
發(fā)布緊急采購，3分鐘左右您將得到回復。