參數(shù)資料
型號(hào)： CY28346
廠商： Cypress Semiconductor Corp.
英文描述： Clock Synthesizer with Differential CPU Outputs
中文描述： 時(shí)鐘合成器的差分輸出的CPU
文件頁(yè)數(shù)： 2/20頁(yè)
文件大?。?/td> 179K
代理商： CY28346
CY28346
Document #: 38-07331 Rev. *B
Page 2 of 20
Pin Description
Pin
2
3
Name
XIN
XOUT
PWR
I/O
I
O
Description
Oscillator Buffer Input
. Connect to a crystal or to an external clock.
Oscillator Buffer Output
. Connect to a crystal. Do not connect when an external
clock is applied at X
IN
.
Differential Host Output Clock Pairs
. See
Table 1
for frequency/functionality.
V
DD
52, 51, 49, 48,
45, 44
10, 11, 12, 13,
16, 17, 18
5, 6, 7
CPUT(0:2),
CPUC(0:2)
PCI(0:6)
V
DD
O
V
DDP
O
PCI Clock Outputs
. Are synchronous to 66IN or 3V66 clock. See
Table 1
.
PCIF (0:2)
V
DD
O
33-MHz PCI Clocks
.
÷
2 copies of 66IN or 3V66 clocks that may be free running
(not stopped when PCI_STP# is asserted LOW) or may be stoppable depending
on the programming of SMBus register Byte3,Bits (3:5).
Buffered Output Copy of the Device
’
s X
IN
Clock
.
Current Reference Programming Input for CPU Buffers
. A resistor is
connected between this pin and VSSIREF.
Qualifying Input that Latches S(0:2) and MULT0
. When this input is at a logic
LOW, the S(0:2) and MULT0 are latched.
Fixed 48-MHz USB Clock Outputs
.
Fixed 48-MHZ DOT Clock Outputs
.
3.3V 66-MHz Fixed-frequency Clock
.
3.3V Clock Selectable with SMBus Byte0,Bit5, When Byte5,Bit5
. When Byte
0,Bit 5 is at a logic 1, then this pin is a 48M output clock. When Byte0,Bit5 is a
logic 0, this is a 66M output clock (default).
Power-down Mode Pin
. A logic LOW level causes the device to enter a
power-down state. All internal logic is turned off except for the SMBus logic. All
output buffers are stopped.
Programming Input Selection for CPU Clock Current Multiplier
.
56
42
REF
IREF
V
DD
V
DD
O
I
28
VTT_PG#
V
DD
I
39
38
33
35
48MUSB
48MDOT
3V66_0
3V66_1/VCH
V
DD48
V
DD48
V
DD
V
DD
O
O
O
O
25
PD#
V
DD
I
PU
43
MULT0
I
PU
I
I
55, 54
29
S(0,1)
SDATA
I
I
Frequency Select Inputs
. See
Table 1
.
Serial Data Input
. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
Serial Clock Input
. Conforms to the SMBus specification.
Frequency Select Input
. See
Table 1
. This is a Tri-level input which is driven
HIGH, LOW or driven to a intermediate level.
PCI Clock Disable Input
. When asserted LOW, PCI (0:6) clocks are synchro-
nously disabled in a LOW state. This pin does not effect PCIF (0:2) clocks
’
outputs if they are programmed to be PCIF clocks via the device
’
s SMBus
interface.
CPU Clock Disable Input
. When asserted LOW, CPUT (0:2) clocks are synchro-
nously disabled in a HIGH state and CPUC(0:2) clocks are synchronously
disabled in a LOW state.
Input Connection for 66CLK(0:2) Output Clock Buffers
if S2 = 1, or output
clock for fixed 66-MHz clock if S2 = 0. See
Table 1
.
3.3V Clock Outputs
. These clocks are buffered copies of the 66IN clock or fixed
at 66 MHz. See
Table 1
.
PWR
3.3V Power Supply
.
30
40
SCLK
S2
I
I
I
T
I
V
DD
34
PCI_STP#
V
DD
PU
53
CPU_STP#
V
DD
I
PU
24
66IN/3V66_5
V
DD
I/O
21, 22, 23
66B(0:2)/
3V66(2:4)
V
DD
V
DD
O
1, 8, 14, 19, 32,
37, 46, 50
4, 9, 15, 20, 27,
31, 36, 47
41
V
SS
PWR
Common Ground
.
V
SS
IREF
PWR
Current Reference Programming Input for CPU Buffers
. A resistor is
connected between this pin and IREF. This pin should also be returned to device
V
SS
.
PWR
Analog Power Input
. Used for phase-locked loops (PLLs) and internal analog
circuits. It is also specifically used to detect and determine when power is at an
acceptable level to enable the device to operate.
26
V
DDA
–
相關(guān)PDF資料
PDF描述
CY28346OC CONN BNC PLUG CRIMP RG-TFE-59,62
CY28346OCT CONN BNC PLUG CRIMP RG-59,62
CY28346ZC Clock Synthesizer with Differential CPU Outputs
CY28346ZCT Clock Synthesizer with Differential CPU Outputs
CY28347 HDC-HA-48-SVL1/29 RoHS Compliant: Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28346_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential CPU Outputs
CY28346-2 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential CPU Outputs
CY28346-2_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential CPU Outputs
CY28346OC 制造商:Rochester Electronics LLC 功能描述:FTG FOR INTEL 830M AND 845 CHIPSETS (CK-408) - Bulk
CY28346OCT 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential CPU Outputs
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*