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參數(shù)資料
| 型號： | CXK77B1841AGB |
| 廠商： | Sony Corporation |
| 英文描述： | 4Mb Late Write LVTTL High Speed Synchronous SRAM (128K x 36Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (128K x 36位)) |
| 中文描述： | 4Mb的后寫入LVTTL高速同步SRAM（128K的x 36Bit）（4分位，寫延遲，LVTTL高速同步靜態(tài)隨機存儲器（128K的× 36位）） |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 222K |
| 代理商： | CXK77B1841AGB |
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4Mb, Sync LW, LVTTL, rev 1.2
4 / 28
September 24, 1998
SONY
CXK77B3641AGB / CXK77B1841AGB
Preliminary
Pin Description
Symbol
Type
Description
SA
Input
Synchronous Address Inputs - Registered on the rising edge of K.
DQa, DQb
DQc, DQd
I/O
Synchronous Data Inputs / Outputs - Registered on the rising edge of K during write operations.
DQa - indicates Data Byte a
DQb - indicates Data Byte b
DQc - indicates Data Byte c
DQd - indicates Data Byte d
K, K
Input
Differential Input Clocks
C, C
Input
Differential Output Control Clocks - Reserved for future use.
SS
Input
Synchronous Select Input - Registered on the rising edge of K.
SS = 0 specifies a Write Operation when SW = 0
specifies a Read Operation when SW = 1
SS = 1 specifies a Deselect Operation
SW
Input
Synchronous Global Write Enable Input - Registered on the rising edge of K.
SW = 0 specifies a Write Operation when SS = 0
SW = 1 specifies a Read Operation when SS = 0
SBWa, SBWb,
SBWc, SBWd
Input
Synchronous Byte Write Enable Inputs - Registered on the rising edge of K.
SBWa = 0 specifies write Data Byte a when SS = 0 and SW = 0
SBWb = 0 specifies write Data Byte b when SS = 0 and SW = 0
SBWc = 0 specifies write Data Byte c when SS = 0 and SW = 0
SBWd = 0 specifies write Data Byte d when SS = 0 and SW = 0
G
Input
Asynchronous Output Enable Input - De-asserted (high) forces the data output drivers to Hi-Z.
ZZ
Input
Asynchronous Sleep Mode Input - Asserted (high) forces the SRAM into low-power mode.
M1, M2
Input
Read Operation Protocol Select - These mode pins must be tied to V
DD
or V
SS
before power-up.
M1:M2 = 00 specifies Register - Flow Thru Read Operations
M1:M2 = 01 specifies Register - Register Read Operations
M1:M2 = 10 specifies Register - Latch Read Operations
M1:M2 = 11 reserved for future use
V
DD
3.3V Core Power Supply - Core supply voltage.
V
DDQ
Output Power Supply - Output buffer supply voltage.
V
SS
Ground
TCK
Input
JTAG Clock
TMS
Input
JTAG Mode Select
TDI
Input
JTAG Data In
TDO
Output
JTAG Data Out
NC
No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these
pins. They can be left unconnected or tied directly to V
DD
or V
SS
.
相關PDF資料 |
PDF描述 |
|---|---|
| CXK77B3641AGB | 4Mb Late Write LVTTL High Speed Synchronous SRAMs (128K x 36Bit)(4M位、寫延遲、高速邏輯收發(fā)（HSTL）、高速同步靜態(tài)RAM (128K x 36位)) |
| CXK77B1841GB | 4Mb Late Write LVTTL High Speed Synchronous SRAM (256K x 18Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (256K x 18位)) |
| CXK77B3611AGB- | High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3611AGB-5 | High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3611AGB-6 | High Speed Bi-CMOS Synchronous Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CXK77B1841GB-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
| CXK77B1841GB-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
| CXK77B3610AGB-5R | 制造商:Sony Batteries 功能描述:77B3610AGB-5R |
| CXK77B3610GB- | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3610GB-6 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:High Speed Bi-CMOS Synchronous Static RAM |
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