參數(shù)資料
型號： CXK77B3641AGB
廠商： Sony Corporation
英文描述： 4Mb Late Write LVTTL High Speed Synchronous SRAMs (128K x 36Bit)(4M位、寫延遲、高速邏輯收發(fā)（HSTL）、高速同步靜態(tài)RAM (128K x 36位))
中文描述： 4Mb的后寫入LVTTL高速（128K的x 36Bit）（4分位，寫延遲，高速邏輯收發(fā)（HSTL），高速同步靜態(tài)隨機存儲器（128K的× 36位）同步靜態(tài)存儲器）
文件頁數(shù)： 1/28頁
文件大小： 222K
代理商： CXK77B3641AGB
4Mb, Sync LW, LVTTL, rev 1.2
1 / 28
September 24, 1998
CXK77B3641AGB / CXK77B1841AGB
SONY
33/37/5/6
4Mb Late Write LVTTL High Speed Synchronous SRAMs (128K x 36 or 256K x 18 Organization)
Preliminary
Description
Features
R-R Mode
t
KHKH
/ t
KHQV
------------------
3.3ns / 2.3ns
3.6ns / 2.4ns
5.0ns / 2.5ns
6.0ns / 2.5ns
R-L, R-FT Modes
t
KHKH
/ t
KHQV
------------------
5.0ns / 5.0ns
5.3ns / 5.3ns
5.3ns / 5.3ns
6.0ns / 6.0ns
Fast Cycle / Access Time
---------------------------------
-33
-37
-5
-6
Single 3.3V power supply (V
DD
): 3.3V
±
5%
Register - Register (R-R), Register - Latch (R-L), or Register - Flow Thru (R-FT) read operations
Read operation protocol selectable via dedicated mode pins (M1, M2)
Fully coherent, late write, self-timed write operations
Byte Write capability
Differential input clocks (K/K)
Asynchronous output enable (G)
Dedicated output supply voltage (V
DDQ
): 2.5V or 3.3V typical
LVTTL/LVCMOS-compatible I/O interface
Sleep (power down) mode via dedicated mode pin (ZZ)
JTAG boundary scan (subset of IEEE standard 1149.1)
119 pin (7x17), 1.27mm pitch, 14mm x 22mm Plastic Ball Grid Array (PBGA) package
The CXK77B3641A (organized as 131,072 words by 36 bits) and the CXK77B1841A (organized as 262,144 words by 18 bits)
are high speed BiCMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input registers,
high speed RAM, output registers/latches, and a one-deep write buffer onto a single monolithic IC. Three distinct read operation
protocols, Register - Register (R-R), Register - Latch (R-L), and Register - Flow Thru (R-FT), and one write operation protocol,
Late Write (LW), are supported, providing a flexible, high-performance user interface.
All address, data, and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the positive edge
of K clock. Read operation protocol is selectable through external mode pins M1 and M2.
Write operations are internally self-timed, eliminating the need for complex off-chip write pulse generation. In Register - Latch
and Register - Flow Thru modes, when SW (Global Write Enable) is driven active, the subsequent positive edge of K clock tri-
states the SRAM’s output drivers immediately, allowing Read-Write-Read operations to be initiated consecutively, with no dead
cycles between them.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 300 MHz operation is obtained from a single
3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
相關(guān)PDF資料
PDF描述
CXK77B1841GB 4Mb Late Write LVTTL High Speed Synchronous SRAM (256K x 18Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (256K x 18位))
CXK77B3611AGB- High Speed Bi-CMOS Synchronous Static RAM
CXK77B3611AGB-5 High Speed Bi-CMOS Synchronous Static RAM
CXK77B3611AGB-6 High Speed Bi-CMOS Synchronous Static RAM
CXK77B3611AGB High Speed 1MBit Bi-CMOS Synchronous Static RAM(高速1M位、Bi-CMOS同步靜態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CXK77B3641GB-5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM
CXK77B3641GB-6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM
CXK77K18R320GB 制造商:SONY 制造商全稱:Sony Corporation 功能描述:32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)
CXK77K18R320GB-3 制造商:SONY 制造商全稱:Sony Corporation 功能描述:32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)
CXK77K18R320GB-33 制造商:SONY 制造商全稱:Sony Corporation 功能描述:32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*